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Name	Size	Permission	Date
cuda_wrappers	[ DIR ]	drwxr-xr-x	2025-06-02 12:56
llvm_libc_wrappers	[ DIR ]	drwxr-xr-x	2025-06-02 12:56
openmp_wrappers	[ DIR ]	drwxr-xr-x	2025-06-02 12:56
ppc_wrappers	[ DIR ]	drwxr-xr-x	2025-06-02 12:56
__clang_cuda_builtin_vars.h	4.78 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_cmath.h	18.06 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_complex_builtins.h	9.36 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_device_functions.h	56.68 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_intrinsics.h	29.93 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_libdevice_declares.h	21.87 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_math.h	15.99 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_math_forward_declares.h	8.27 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_runtime_wrapper.h	17.61 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_texture_intrinsics.h	31.86 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_cmath.h	26.34 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_libdevice_declares.h	19.87 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_math.h	31.96 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_runtime_wrapper.h	4.65 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_stdlib.h	1.19 KB	-rw-r--r--	2023-11-28 08:52
__stddef_max_align_t.h	857 B	-rw-r--r--	2023-11-28 08:52
__wmmintrin_aes.h	5.15 KB	-rw-r--r--	2023-11-28 08:52
__wmmintrin_pclmul.h	1.99 KB	-rw-r--r--	2023-11-28 08:52
adxintrin.h	7.37 KB	-rw-r--r--	2023-11-28 08:52
altivec.h	697.32 KB	-rw-r--r--	2023-11-28 08:52
ammintrin.h	7.54 KB	-rw-r--r--	2023-11-28 08:52
amxcomplexintrin.h	6.81 KB	-rw-r--r--	2023-11-28 08:52
amxfp16intrin.h	1.82 KB	-rw-r--r--	2023-11-28 08:52
amxintrin.h	21.12 KB	-rw-r--r--	2023-11-28 08:52
arm64intr.h	993 B	-rw-r--r--	2023-11-28 08:52
arm_acle.h	25.66 KB	-rw-r--r--	2023-11-28 08:52
arm_bf16.h	548 B	-rw-r--r--	2024-11-06 08:03
arm_cde.h	32.67 KB	-rw-r--r--	2024-11-06 08:03
arm_cmse.h	6.21 KB	-rw-r--r--	2023-11-28 08:52
arm_fp16.h	16.92 KB	-rw-r--r--	2024-11-06 08:03
arm_mve.h	1.48 MB	-rw-r--r--	2024-11-06 08:03
arm_neon.h	2.45 MB	-rw-r--r--	2024-11-06 08:03
arm_neon_sve_bridge.h	9.48 KB	-rw-r--r--	2023-11-28 08:52
arm_sme_draft_spec_subject_to_change.h	60.2 KB	-rw-r--r--	2024-11-06 08:03
arm_sve.h	1.51 MB	-rw-r--r--	2024-11-06 08:03
armintr.h	843 B	-rw-r--r--	2023-11-28 08:52
avx2intrin.h	186.96 KB	-rw-r--r--	2023-11-28 08:52
avx512bf16intrin.h	10.51 KB	-rw-r--r--	2023-11-28 08:52
avx512bitalgintrin.h	2.41 KB	-rw-r--r--	2023-11-28 08:52
avx512bwintrin.h	75.33 KB	-rw-r--r--	2023-11-28 08:52
avx512cdintrin.h	4.12 KB	-rw-r--r--	2023-11-28 08:52
avx512dqintrin.h	58.75 KB	-rw-r--r--	2023-11-28 08:52
avx512erintrin.h	11.83 KB	-rw-r--r--	2023-11-28 08:52
avx512fintrin.h	382.64 KB	-rw-r--r--	2023-11-28 08:52
avx512fp16intrin.h	156.63 KB	-rw-r--r--	2023-11-28 08:52
avx512ifmaintrin.h	2.49 KB	-rw-r--r--	2023-11-28 08:52
avx512ifmavlintrin.h	4.31 KB	-rw-r--r--	2023-11-28 08:52
avx512pfintrin.h	4.53 KB	-rw-r--r--	2023-11-28 08:52
avx512vbmi2intrin.h	13.17 KB	-rw-r--r--	2023-11-28 08:52
avx512vbmiintrin.h	3.72 KB	-rw-r--r--	2023-11-28 08:52
avx512vbmivlintrin.h	6.94 KB	-rw-r--r--	2023-11-28 08:52
avx512vlbf16intrin.h	19.21 KB	-rw-r--r--	2023-11-28 08:52
avx512vlbitalgintrin.h	4.23 KB	-rw-r--r--	2023-11-28 08:52
avx512vlbwintrin.h	121.26 KB	-rw-r--r--	2023-11-28 08:52
avx512vlcdintrin.h	7.66 KB	-rw-r--r--	2023-11-28 08:52
avx512vldqintrin.h	46.41 KB	-rw-r--r--	2023-11-28 08:52
avx512vlfp16intrin.h	85.51 KB	-rw-r--r--	2023-11-28 08:52
avx512vlintrin.h	322.29 KB	-rw-r--r--	2023-11-28 08:52
avx512vlvbmi2intrin.h	25.72 KB	-rw-r--r--	2023-11-28 08:52
avx512vlvnniintrin.h	13.13 KB	-rw-r--r--	2023-11-28 08:52
avx512vlvp2intersectintrin.h	4.44 KB	-rw-r--r--	2023-11-28 08:52
avx512vnniintrin.h	4.21 KB	-rw-r--r--	2023-11-28 08:52
avx512vp2intersectintrin.h	2.9 KB	-rw-r--r--	2023-11-28 08:52
avx512vpopcntdqintrin.h	2 KB	-rw-r--r--	2023-11-28 08:52
avx512vpopcntdqvlintrin.h	3.31 KB	-rw-r--r--	2023-11-28 08:52
avxifmaintrin.h	5.75 KB	-rw-r--r--	2023-11-28 08:52
avxintrin.h	195.41 KB	-rw-r--r--	2023-11-28 08:52
avxneconvertintrin.h	14.09 KB	-rw-r--r--	2023-11-28 08:52
avxvnniint16intrin.h	17.41 KB	-rw-r--r--	2023-11-28 08:52
avxvnniint8intrin.h	18.67 KB	-rw-r--r--	2023-11-28 08:52
avxvnniintrin.h	10.44 KB	-rw-r--r--	2023-11-28 08:52
bmi2intrin.h	7.09 KB	-rw-r--r--	2023-11-28 08:52
bmiintrin.h	14.12 KB	-rw-r--r--	2023-11-28 08:52
builtins.h	741 B	-rw-r--r--	2023-11-28 08:52
cet.h	1.49 KB	-rw-r--r--	2023-11-28 08:52
cetintrin.h	3.27 KB	-rw-r--r--	2023-11-28 08:52
cldemoteintrin.h	1.18 KB	-rw-r--r--	2023-11-28 08:52
clflushoptintrin.h	1.17 KB	-rw-r--r--	2023-11-28 08:52
clwbintrin.h	1.2 KB	-rw-r--r--	2023-11-28 08:52
clzerointrin.h	1.19 KB	-rw-r--r--	2023-11-28 08:52
cmpccxaddintrin.h	2.33 KB	-rw-r--r--	2023-11-28 08:52
cpuid.h	11.01 KB	-rw-r--r--	2023-11-28 08:52
crc32intrin.h	3.27 KB	-rw-r--r--	2023-11-28 08:52
emmintrin.h	192.64 KB	-rw-r--r--	2023-11-28 08:52
enqcmdintrin.h	2.12 KB	-rw-r--r--	2023-11-28 08:52
f16cintrin.h	5.39 KB	-rw-r--r--	2023-11-28 08:52
float.h	5.63 KB	-rw-r--r--	2023-11-28 08:52
fma4intrin.h	6.82 KB	-rw-r--r--	2023-11-28 08:52
fmaintrin.h	28.4 KB	-rw-r--r--	2023-11-28 08:52
fxsrintrin.h	2.82 KB	-rw-r--r--	2023-11-28 08:52
gfniintrin.h	7.57 KB	-rw-r--r--	2023-11-28 08:52
hexagon_circ_brev_intrinsics.h	15.59 KB	-rw-r--r--	2023-11-28 08:52
hexagon_protos.h	374.42 KB	-rw-r--r--	2023-11-28 08:52
hexagon_types.h	130.33 KB	-rw-r--r--	2023-11-28 08:52
hresetintrin.h	1.36 KB	-rw-r--r--	2023-11-28 08:52
htmintrin.h	6.14 KB	-rw-r--r--	2023-11-28 08:52
htmxlintrin.h	9.01 KB	-rw-r--r--	2023-11-28 08:52
hvx_hexagon_protos.h	254.26 KB	-rw-r--r--	2023-11-28 08:52
ia32intrin.h	12.72 KB	-rw-r--r--	2023-11-28 08:52
immintrin.h	23.57 KB	-rw-r--r--	2023-11-28 08:52
intrin.h	28.22 KB	-rw-r--r--	2023-11-28 08:52
inttypes.h	2.26 KB	-rw-r--r--	2023-11-28 08:52
invpcidintrin.h	764 B	-rw-r--r--	2023-11-28 08:52
iso646.h	656 B	-rw-r--r--	2023-11-28 08:52
keylockerintrin.h	17.98 KB	-rw-r--r--	2023-11-28 08:52
larchintrin.h	7.8 KB	-rw-r--r--	2023-11-28 08:52
limits.h	3.61 KB	-rw-r--r--	2023-11-28 08:52
lwpintrin.h	5 KB	-rw-r--r--	2023-11-28 08:52
lzcntintrin.h	3.18 KB	-rw-r--r--	2023-11-28 08:52
mm3dnow.h	4.5 KB	-rw-r--r--	2023-11-28 08:52
mm_malloc.h	1.88 KB	-rw-r--r--	2023-11-28 08:52
mmintrin.h	55.98 KB	-rw-r--r--	2023-11-28 08:52
module.modulemap	3.33 KB	-rw-r--r--	2023-11-28 08:52
movdirintrin.h	1.57 KB	-rw-r--r--	2023-11-28 08:52
msa.h	25.01 KB	-rw-r--r--	2023-11-28 08:52
mwaitxintrin.h	2.19 KB	-rw-r--r--	2023-11-28 08:52
nmmintrin.h	709 B	-rw-r--r--	2023-11-28 08:52
opencl-c-base.h	30.38 KB	-rw-r--r--	2023-11-28 08:52
opencl-c.h	874.39 KB	-rw-r--r--	2023-11-28 08:52
pconfigintrin.h	1.19 KB	-rw-r--r--	2023-11-28 08:52
pkuintrin.h	934 B	-rw-r--r--	2023-11-28 08:52
pmmintrin.h	10.5 KB	-rw-r--r--	2023-11-28 08:52
popcntintrin.h	1.82 KB	-rw-r--r--	2023-11-28 08:52
prfchiintrin.h	2.02 KB	-rw-r--r--	2023-11-28 08:52
prfchwintrin.h	2.06 KB	-rw-r--r--	2023-11-28 08:52
ptwriteintrin.h	1.05 KB	-rw-r--r--	2023-11-28 08:52
raointintrin.h	6.59 KB	-rw-r--r--	2023-11-28 08:52
rdpruintrin.h	1.59 KB	-rw-r--r--	2023-11-28 08:52
rdseedintrin.h	2.85 KB	-rw-r--r--	2023-11-28 08:52
riscv_ntlh.h	855 B	-rw-r--r--	2023-11-28 08:52
rtmintrin.h	1.25 KB	-rw-r--r--	2023-11-28 08:52
s390intrin.h	604 B	-rw-r--r--	2023-11-28 08:52
serializeintrin.h	881 B	-rw-r--r--	2023-11-28 08:52
sgxintrin.h	1.77 KB	-rw-r--r--	2023-11-28 08:52
sha512intrin.h	5.95 KB	-rw-r--r--	2023-11-28 08:52
shaintrin.h	7.37 KB	-rw-r--r--	2023-11-28 08:52
sifive_vector.h	522 B	-rw-r--r--	2023-11-28 08:52
sm3intrin.h	7.29 KB	-rw-r--r--	2023-11-28 08:52
sm4intrin.h	8.2 KB	-rw-r--r--	2023-11-28 08:52
smmintrin.h	99.32 KB	-rw-r--r--	2023-11-28 08:52
stdalign.h	911 B	-rw-r--r--	2023-11-28 08:52
stdarg.h	1.66 KB	-rw-r--r--	2023-11-28 08:52
stdatomic.h	8.3 KB	-rw-r--r--	2023-11-28 08:52
stdbool.h	1.04 KB	-rw-r--r--	2023-11-28 08:52
stddef.h	4.16 KB	-rw-r--r--	2023-11-28 08:52
stdint.h	32.49 KB	-rw-r--r--	2023-11-28 08:52
stdnoreturn.h	1.17 KB	-rw-r--r--	2023-11-28 08:52
tbmintrin.h	3.15 KB	-rw-r--r--	2023-11-28 08:52
tgmath.h	29.68 KB	-rw-r--r--	2023-11-28 08:52
tmmintrin.h	29.51 KB	-rw-r--r--	2023-11-28 08:52
tsxldtrkintrin.h	1.97 KB	-rw-r--r--	2023-11-28 08:52
uintrintrin.h	4.96 KB	-rw-r--r--	2023-11-28 08:52
unwind.h	11.21 KB	-rw-r--r--	2023-11-28 08:52
vadefs.h	1.39 KB	-rw-r--r--	2023-11-28 08:52
vaesintrin.h	2.46 KB	-rw-r--r--	2023-11-28 08:52
varargs.h	477 B	-rw-r--r--	2023-11-28 08:52
vecintrin.h	360.82 KB	-rw-r--r--	2023-11-28 08:52
velintrin.h	2.1 KB	-rw-r--r--	2023-11-28 08:52
velintrin_approx.h	3.54 KB	-rw-r--r--	2023-11-28 08:52
velintrin_gen.h	69.06 KB	-rw-r--r--	2023-11-28 08:52
vpclmulqdqintrin.h	1.06 KB	-rw-r--r--	2023-11-28 08:52
waitpkgintrin.h	1.33 KB	-rw-r--r--	2023-11-28 08:52
wasm_simd128.h	76.25 KB	-rw-r--r--	2023-11-28 08:52
wbnoinvdintrin.h	749 B	-rw-r--r--	2023-11-28 08:52
wmmintrin.h	659 B	-rw-r--r--	2023-11-28 08:52
x86gprintrin.h	2.32 KB	-rw-r--r--	2023-11-28 08:52
x86intrin.h	1.81 KB	-rw-r--r--	2023-11-28 08:52
xmmintrin.h	106.73 KB	-rw-r--r--	2023-11-28 08:52
xopintrin.h	19.96 KB	-rw-r--r--	2023-11-28 08:52
xsavecintrin.h	2.51 KB	-rw-r--r--	2023-11-28 08:52
xsaveintrin.h	1.64 KB	-rw-r--r--	2023-11-28 08:52
xsaveoptintrin.h	1 KB	-rw-r--r--	2023-11-28 08:52
xsavesintrin.h	1.24 KB	-rw-r--r--	2023-11-28 08:52
xtestintrin.h	873 B	-rw-r--r--	2023-11-28 08:52

Rename

/*===---- immintrin.h - Intel intrinsics -----------------------------------===
 *
 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 * See https://llvm.org/LICENSE.txt for license information.
 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 *
 *===-----------------------------------------------------------------------===
 */

#ifndef __IMMINTRIN_H
#define __IMMINTRIN_H

#if !defined(__i386__) && !defined(__x86_64__)
#error "This header is only meant to be used on x86 and x64 architecture"
#endif

#include <x86gprintrin.h>

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__MMX__)
#include <mmintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SSE__)
#include <xmmintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SSE2__)
#include <emmintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SSE3__)
#include <pmmintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SSSE3__)
#include <tmmintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__SSE4_2__) || defined(__SSE4_1__))
#include <smmintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AES__) || defined(__PCLMUL__))
#include <wmmintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__CLFLUSHOPT__)
#include <clflushoptintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__CLWB__)
#include <clwbintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX__)
#include <avxintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX2__)
#include <avx2intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__F16C__)
#include <f16cintrin.h>
#endif

/* No feature check desired due to internal checks */
#include <bmiintrin.h>

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__BMI2__)
#include <bmi2intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__LZCNT__)
#include <lzcntintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__POPCNT__)
#include <popcntintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__FMA__)
#include <fmaintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512F__)
#include <avx512fintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512VL__)
#include <avx512vlintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512BW__)
#include <avx512bwintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512BITALG__)
#include <avx512bitalgintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512CD__)
#include <avx512cdintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512VPOPCNTDQ__)
#include <avx512vpopcntdqintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512VPOPCNTDQ__))
#include <avx512vpopcntdqvlintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512VNNI__)
#include <avx512vnniintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512VNNI__))
#include <avx512vlvnniintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVXVNNI__)
#include <avxvnniintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512DQ__)
#include <avx512dqintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512BITALG__))
#include <avx512vlbitalgintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512BW__))
#include <avx512vlbwintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512CD__))
#include <avx512vlcdintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512DQ__))
#include <avx512vldqintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512ER__)
#include <avx512erintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512IFMA__)
#include <avx512ifmaintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512IFMA__) && defined(__AVX512VL__))
#include <avx512ifmavlintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVXIFMA__)
#include <avxifmaintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512VBMI__)
#include <avx512vbmiintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VBMI__) && defined(__AVX512VL__))
#include <avx512vbmivlintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512VBMI2__)
#include <avx512vbmi2intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VBMI2__) && defined(__AVX512VL__))
#include <avx512vlvbmi2intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512PF__)
#include <avx512pfintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512FP16__)
#include <avx512fp16intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512FP16__))
#include <avx512vlfp16intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512BF16__)
#include <avx512bf16intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512BF16__))
#include <avx512vlbf16intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__PKU__)
#include <pkuintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__VPCLMULQDQ__)
#include <vpclmulqdqintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__VAES__)
#include <vaesintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__GFNI__)
#include <gfniintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVXVNNIINT8__)
#include <avxvnniint8intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVXNECONVERT__)
#include <avxneconvertintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SHA512__)
#include <sha512intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SM3__)
#include <sm3intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SM4__)
#include <sm4intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVXVNNIINT16__)
#include <avxvnniint16intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__RDPID__)
/// Returns the value of the IA32_TSC_AUX MSR (0xc0000103).
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> RDPID </c> instruction.
static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__, __target__("rdpid")))
_rdpid_u32(void) {
  return __builtin_ia32_rdpid();
}
#endif // __RDPID__

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__RDRND__)
/// Returns a 16-bit hardware-generated random value.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> RDRAND </c> instruction.
///
/// \param __p
///    A pointer to a 16-bit memory location to place the random value.
/// \returns 1 if the value was successfully generated, 0 otherwise.
static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
_rdrand16_step(unsigned short *__p)
{
  return (int)__builtin_ia32_rdrand16_step(__p);
}

/// Returns a 32-bit hardware-generated random value.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> RDRAND </c> instruction.
///
/// \param __p
///    A pointer to a 32-bit memory location to place the random value.
/// \returns 1 if the value was successfully generated, 0 otherwise.
static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
_rdrand32_step(unsigned int *__p)
{
  return (int)__builtin_ia32_rdrand32_step(__p);
}

/// Returns a 64-bit hardware-generated random value.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> RDRAND </c> instruction.
///
/// \param __p
///    A pointer to a 64-bit memory location to place the random value.
/// \returns 1 if the value was successfully generated, 0 otherwise.
static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("rdrnd")))
_rdrand64_step(unsigned long long *__p)
{
#ifdef __x86_64__
  return (int)__builtin_ia32_rdrand64_step(__p);
#else
  // We need to emulate the functionality of 64-bit rdrand with 2 32-bit
  // rdrand instructions.
  unsigned int __lo, __hi;
  unsigned int __res_lo = __builtin_ia32_rdrand32_step(&__lo);
  unsigned int __res_hi = __builtin_ia32_rdrand32_step(&__hi);
  if (__res_lo && __res_hi) {
    *__p = ((unsigned long long)__hi << 32) | (unsigned long long)__lo;
    return 1;
  } else {
    *__p = 0;
    return 0;
  }
#endif
}
#endif /* __RDRND__ */

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__FSGSBASE__)
#ifdef __x86_64__
/// Reads the FS base register.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> RDFSBASE </c> instruction.
///
/// \returns The lower 32 bits of the FS base register.
static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
_readfsbase_u32(void)
{
  return __builtin_ia32_rdfsbase32();
}

/// Reads the FS base register.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> RDFSBASE </c> instruction.
///
/// \returns The contents of the FS base register.
static __inline__ unsigned long long __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
_readfsbase_u64(void)
{
  return __builtin_ia32_rdfsbase64();
}

/// Reads the GS base register.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> RDGSBASE </c> instruction.
///
/// \returns The lower 32 bits of the GS base register.
static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
_readgsbase_u32(void)
{
  return __builtin_ia32_rdgsbase32();
}

/// Reads the GS base register.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> RDGSBASE </c> instruction.
///
/// \returns The contents of the GS base register.
static __inline__ unsigned long long __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
_readgsbase_u64(void)
{
  return __builtin_ia32_rdgsbase64();
}

/// Modifies the FS base register.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> WRFSBASE </c> instruction.
///
/// \param __V
///    Value to use for the lower 32 bits of the FS base register.
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
_writefsbase_u32(unsigned int __V)
{
  __builtin_ia32_wrfsbase32(__V);
}

/// Modifies the FS base register.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> WRFSBASE </c> instruction.
///
/// \param __V
///    Value to use for the FS base register.
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
_writefsbase_u64(unsigned long long __V)
{
  __builtin_ia32_wrfsbase64(__V);
}

/// Modifies the GS base register.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> WRGSBASE </c> instruction.
///
/// \param __V
///    Value to use for the lower 32 bits of the GS base register.
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
_writegsbase_u32(unsigned int __V)
{
  __builtin_ia32_wrgsbase32(__V);
}

/// Modifies the GS base register.
///
/// \headerfile <immintrin.h>
///
/// This intrinsic corresponds to the <c> WRFSBASE </c> instruction.
///
/// \param __V
///    Value to use for GS base register.
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
_writegsbase_u64(unsigned long long __V)
{
  __builtin_ia32_wrgsbase64(__V);
}

#endif
#endif /* __FSGSBASE__ */

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__MOVBE__)

/* The structs used below are to force the load/store to be unaligned. This
 * is accomplished with the __packed__ attribute. The __may_alias__ prevents
 * tbaa metadata from being generated based on the struct and the type of the
 * field inside of it.
 */

static __inline__ short __attribute__((__always_inline__, __nodebug__, __target__("movbe")))
_loadbe_i16(void const * __P) {
  struct __loadu_i16 {
    unsigned short __v;
  } __attribute__((__packed__, __may_alias__));
  return (short)__builtin_bswap16(((const struct __loadu_i16*)__P)->__v);
}

static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("movbe")))
_storebe_i16(void * __P, short __D) {
  struct __storeu_i16 {
    unsigned short __v;
  } __attribute__((__packed__, __may_alias__));
  ((struct __storeu_i16*)__P)->__v = __builtin_bswap16((unsigned short)__D);
}

static __inline__ int __attribute__((__always_inline__, __nodebug__, __target__("movbe")))
_loadbe_i32(void const * __P) {
  struct __loadu_i32 {
    unsigned int __v;
  } __attribute__((__packed__, __may_alias__));
  return (int)__builtin_bswap32(((const struct __loadu_i32*)__P)->__v);
}

static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("movbe")))
_storebe_i32(void * __P, int __D) {
  struct __storeu_i32 {
    unsigned int __v;
  } __attribute__((__packed__, __may_alias__));
  ((struct __storeu_i32*)__P)->__v = __builtin_bswap32((unsigned int)__D);
}

#ifdef __x86_64__
static __inline__ long long __attribute__((__always_inline__, __nodebug__, __target__("movbe")))
_loadbe_i64(void const * __P) {
  struct __loadu_i64 {
    unsigned long long __v;
  } __attribute__((__packed__, __may_alias__));
  return (long long)__builtin_bswap64(((const struct __loadu_i64*)__P)->__v);
}

static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("movbe")))
_storebe_i64(void * __P, long long __D) {
  struct __storeu_i64 {
    unsigned long long __v;
  } __attribute__((__packed__, __may_alias__));
  ((struct __storeu_i64*)__P)->__v = __builtin_bswap64((unsigned long long)__D);
}
#endif
#endif /* __MOVBE */

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__RTM__)
#include <rtmintrin.h>
#include <xtestintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SHA__)
#include <shaintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__FXSR__)
#include <fxsrintrin.h>
#endif

/* No feature check desired due to internal MSC_VER checks */
#include <xsaveintrin.h>

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__XSAVEOPT__)
#include <xsaveoptintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__XSAVEC__)
#include <xsavecintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__XSAVES__)
#include <xsavesintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SHSTK__)
#include <cetintrin.h>
#endif

/* Some intrinsics inside adxintrin.h are available only on processors with ADX,
 * whereas others are also available at all times. */
#include <adxintrin.h>

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__RDSEED__)
#include <rdseedintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__WBNOINVD__)
#include <wbnoinvdintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__CLDEMOTE__)
#include <cldemoteintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__WAITPKG__)
#include <waitpkgintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__MOVDIRI__) || defined(__MOVDIR64B__)
#include <movdirintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__PCONFIG__)
#include <pconfigintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SGX__)
#include <sgxintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__PTWRITE__)
#include <ptwriteintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__INVPCID__)
#include <invpcidintrin.h>
#endif
#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AMX_FP16__)
#include <amxfp16intrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__KL__) || defined(__WIDEKL__)
#include <keylockerintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AMX_TILE__) || defined(__AMX_INT8__) || defined(__AMX_BF16__)
#include <amxintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AMX_COMPLEX__)
#include <amxcomplexintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__AVX512VP2INTERSECT__)
#include <avx512vp2intersectintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    (defined(__AVX512VL__) && defined(__AVX512VP2INTERSECT__))
#include <avx512vlvp2intersectintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__ENQCMD__)
#include <enqcmdintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__SERIALIZE__)
#include <serializeintrin.h>
#endif

#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) ||      \
    defined(__TSXLDTRK__)
#include <tsxldtrkintrin.h>
#endif

#if defined(_MSC_VER) && __has_extension(gnu_asm)
/* Define the default attributes for these intrinsics */
#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))
#ifdef __cplusplus
extern "C" {
#endif
/*----------------------------------------------------------------------------*\
|* Interlocked Exchange HLE
\*----------------------------------------------------------------------------*/
#if defined(__i386__) || defined(__x86_64__)
static __inline__ long __DEFAULT_FN_ATTRS
_InterlockedExchange_HLEAcquire(long volatile *_Target, long _Value) {
  __asm__ __volatile__(".byte 0xf2 ; lock ; xchg {%0, %1|%1, %0}"
                       : "+r" (_Value), "+m" (*_Target) :: "memory");
  return _Value;
}
static __inline__ long __DEFAULT_FN_ATTRS
_InterlockedExchange_HLERelease(long volatile *_Target, long _Value) {
  __asm__ __volatile__(".byte 0xf3 ; lock ; xchg {%0, %1|%1, %0}"
                       : "+r" (_Value), "+m" (*_Target) :: "memory");
  return _Value;
}
#endif
#if defined(__x86_64__)
static __inline__ __int64 __DEFAULT_FN_ATTRS
_InterlockedExchange64_HLEAcquire(__int64 volatile *_Target, __int64 _Value) {
  __asm__ __volatile__(".byte 0xf2 ; lock ; xchg {%0, %1|%1, %0}"
                       : "+r" (_Value), "+m" (*_Target) :: "memory");
  return _Value;
}
static __inline__ __int64 __DEFAULT_FN_ATTRS
_InterlockedExchange64_HLERelease(__int64 volatile *_Target, __int64 _Value) {
  __asm__ __volatile__(".byte 0xf3 ; lock ; xchg {%0, %1|%1, %0}"
                       : "+r" (_Value), "+m" (*_Target) :: "memory");
  return _Value;
}
#endif
/*----------------------------------------------------------------------------*\
|* Interlocked Compare Exchange HLE
\*----------------------------------------------------------------------------*/
#if defined(__i386__) || defined(__x86_64__)
static __inline__ long __DEFAULT_FN_ATTRS
_InterlockedCompareExchange_HLEAcquire(long volatile *_Destination,
                              long _Exchange, long _Comparand) {
  __asm__ __volatile__(".byte 0xf2 ; lock ; cmpxchg {%2, %1|%1, %2}"
                       : "+a" (_Comparand), "+m" (*_Destination)
                       : "r" (_Exchange) : "memory");
  return _Comparand;
}
static __inline__ long __DEFAULT_FN_ATTRS
_InterlockedCompareExchange_HLERelease(long volatile *_Destination,
                              long _Exchange, long _Comparand) {
  __asm__ __volatile__(".byte 0xf3 ; lock ; cmpxchg {%2, %1|%1, %2}"
                       : "+a" (_Comparand), "+m" (*_Destination)
                       : "r" (_Exchange) : "memory");
  return _Comparand;
}
#endif
#if defined(__x86_64__)
static __inline__ __int64 __DEFAULT_FN_ATTRS
_InterlockedCompareExchange64_HLEAcquire(__int64 volatile *_Destination,
                              __int64 _Exchange, __int64 _Comparand) {
  __asm__ __volatile__(".byte 0xf2 ; lock ; cmpxchg {%2, %1|%1, %2}"
                       : "+a" (_Comparand), "+m" (*_Destination)
                       : "r" (_Exchange) : "memory");
  return _Comparand;
}
static __inline__ __int64 __DEFAULT_FN_ATTRS
_InterlockedCompareExchange64_HLERelease(__int64 volatile *_Destination,
                              __int64 _Exchange, __int64 _Comparand) {
  __asm__ __volatile__(".byte 0xf3 ; lock ; cmpxchg {%2, %1|%1, %2}"
                       : "+a" (_Comparand), "+m" (*_Destination)
                       : "r" (_Exchange) : "memory");
  return _Comparand;
}
#endif
#ifdef __cplusplus
}
#endif

#undef __DEFAULT_FN_ATTRS

#endif /* defined(_MSC_VER) && __has_extension(gnu_asm) */

#endif /* __IMMINTRIN_H */