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Name	Size	Permission	Date
cuda_wrappers	[ DIR ]	drwxr-xr-x	2025-06-02 12:56
llvm_libc_wrappers	[ DIR ]	drwxr-xr-x	2025-06-02 12:56
openmp_wrappers	[ DIR ]	drwxr-xr-x	2025-06-02 12:56
ppc_wrappers	[ DIR ]	drwxr-xr-x	2025-06-02 12:56
__clang_cuda_builtin_vars.h	4.78 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_cmath.h	18.06 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_complex_builtins.h	9.36 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_device_functions.h	56.68 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_intrinsics.h	29.93 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_libdevice_declares.h	21.87 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_math.h	15.99 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_math_forward_declares.h	8.27 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_runtime_wrapper.h	17.61 KB	-rw-r--r--	2023-11-28 08:52
__clang_cuda_texture_intrinsics.h	31.86 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_cmath.h	26.34 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_libdevice_declares.h	19.87 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_math.h	31.96 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_runtime_wrapper.h	4.65 KB	-rw-r--r--	2023-11-28 08:52
__clang_hip_stdlib.h	1.19 KB	-rw-r--r--	2023-11-28 08:52
__stddef_max_align_t.h	857 B	-rw-r--r--	2023-11-28 08:52
__wmmintrin_aes.h	5.15 KB	-rw-r--r--	2023-11-28 08:52
__wmmintrin_pclmul.h	1.99 KB	-rw-r--r--	2023-11-28 08:52
adxintrin.h	7.37 KB	-rw-r--r--	2023-11-28 08:52
altivec.h	697.32 KB	-rw-r--r--	2023-11-28 08:52
ammintrin.h	7.54 KB	-rw-r--r--	2023-11-28 08:52
amxcomplexintrin.h	6.81 KB	-rw-r--r--	2023-11-28 08:52
amxfp16intrin.h	1.82 KB	-rw-r--r--	2023-11-28 08:52
amxintrin.h	21.12 KB	-rw-r--r--	2023-11-28 08:52
arm64intr.h	993 B	-rw-r--r--	2023-11-28 08:52
arm_acle.h	25.66 KB	-rw-r--r--	2023-11-28 08:52
arm_bf16.h	548 B	-rw-r--r--	2024-11-06 08:03
arm_cde.h	32.67 KB	-rw-r--r--	2024-11-06 08:03
arm_cmse.h	6.21 KB	-rw-r--r--	2023-11-28 08:52
arm_fp16.h	16.92 KB	-rw-r--r--	2024-11-06 08:03
arm_mve.h	1.48 MB	-rw-r--r--	2024-11-06 08:03
arm_neon.h	2.45 MB	-rw-r--r--	2024-11-06 08:03
arm_neon_sve_bridge.h	9.48 KB	-rw-r--r--	2023-11-28 08:52
arm_sme_draft_spec_subject_to_change.h	60.2 KB	-rw-r--r--	2024-11-06 08:03
arm_sve.h	1.51 MB	-rw-r--r--	2024-11-06 08:03
armintr.h	843 B	-rw-r--r--	2023-11-28 08:52
avx2intrin.h	186.96 KB	-rw-r--r--	2023-11-28 08:52
avx512bf16intrin.h	10.51 KB	-rw-r--r--	2023-11-28 08:52
avx512bitalgintrin.h	2.41 KB	-rw-r--r--	2023-11-28 08:52
avx512bwintrin.h	75.33 KB	-rw-r--r--	2023-11-28 08:52
avx512cdintrin.h	4.12 KB	-rw-r--r--	2023-11-28 08:52
avx512dqintrin.h	58.75 KB	-rw-r--r--	2023-11-28 08:52
avx512erintrin.h	11.83 KB	-rw-r--r--	2023-11-28 08:52
avx512fintrin.h	382.64 KB	-rw-r--r--	2023-11-28 08:52
avx512fp16intrin.h	156.63 KB	-rw-r--r--	2023-11-28 08:52
avx512ifmaintrin.h	2.49 KB	-rw-r--r--	2023-11-28 08:52
avx512ifmavlintrin.h	4.31 KB	-rw-r--r--	2023-11-28 08:52
avx512pfintrin.h	4.53 KB	-rw-r--r--	2023-11-28 08:52
avx512vbmi2intrin.h	13.17 KB	-rw-r--r--	2023-11-28 08:52
avx512vbmiintrin.h	3.72 KB	-rw-r--r--	2023-11-28 08:52
avx512vbmivlintrin.h	6.94 KB	-rw-r--r--	2023-11-28 08:52
avx512vlbf16intrin.h	19.21 KB	-rw-r--r--	2023-11-28 08:52
avx512vlbitalgintrin.h	4.23 KB	-rw-r--r--	2023-11-28 08:52
avx512vlbwintrin.h	121.26 KB	-rw-r--r--	2023-11-28 08:52
avx512vlcdintrin.h	7.66 KB	-rw-r--r--	2023-11-28 08:52
avx512vldqintrin.h	46.41 KB	-rw-r--r--	2023-11-28 08:52
avx512vlfp16intrin.h	85.51 KB	-rw-r--r--	2023-11-28 08:52
avx512vlintrin.h	322.29 KB	-rw-r--r--	2023-11-28 08:52
avx512vlvbmi2intrin.h	25.72 KB	-rw-r--r--	2023-11-28 08:52
avx512vlvnniintrin.h	13.13 KB	-rw-r--r--	2023-11-28 08:52
avx512vlvp2intersectintrin.h	4.44 KB	-rw-r--r--	2023-11-28 08:52
avx512vnniintrin.h	4.21 KB	-rw-r--r--	2023-11-28 08:52
avx512vp2intersectintrin.h	2.9 KB	-rw-r--r--	2023-11-28 08:52
avx512vpopcntdqintrin.h	2 KB	-rw-r--r--	2023-11-28 08:52
avx512vpopcntdqvlintrin.h	3.31 KB	-rw-r--r--	2023-11-28 08:52
avxifmaintrin.h	5.75 KB	-rw-r--r--	2023-11-28 08:52
avxintrin.h	195.41 KB	-rw-r--r--	2023-11-28 08:52
avxneconvertintrin.h	14.09 KB	-rw-r--r--	2023-11-28 08:52
avxvnniint16intrin.h	17.41 KB	-rw-r--r--	2023-11-28 08:52
avxvnniint8intrin.h	18.67 KB	-rw-r--r--	2023-11-28 08:52
avxvnniintrin.h	10.44 KB	-rw-r--r--	2023-11-28 08:52
bmi2intrin.h	7.09 KB	-rw-r--r--	2023-11-28 08:52
bmiintrin.h	14.12 KB	-rw-r--r--	2023-11-28 08:52
builtins.h	741 B	-rw-r--r--	2023-11-28 08:52
cet.h	1.49 KB	-rw-r--r--	2023-11-28 08:52
cetintrin.h	3.27 KB	-rw-r--r--	2023-11-28 08:52
cldemoteintrin.h	1.18 KB	-rw-r--r--	2023-11-28 08:52
clflushoptintrin.h	1.17 KB	-rw-r--r--	2023-11-28 08:52
clwbintrin.h	1.2 KB	-rw-r--r--	2023-11-28 08:52
clzerointrin.h	1.19 KB	-rw-r--r--	2023-11-28 08:52
cmpccxaddintrin.h	2.33 KB	-rw-r--r--	2023-11-28 08:52
cpuid.h	11.01 KB	-rw-r--r--	2023-11-28 08:52
crc32intrin.h	3.27 KB	-rw-r--r--	2023-11-28 08:52
emmintrin.h	192.64 KB	-rw-r--r--	2023-11-28 08:52
enqcmdintrin.h	2.12 KB	-rw-r--r--	2023-11-28 08:52
f16cintrin.h	5.39 KB	-rw-r--r--	2023-11-28 08:52
float.h	5.63 KB	-rw-r--r--	2023-11-28 08:52
fma4intrin.h	6.82 KB	-rw-r--r--	2023-11-28 08:52
fmaintrin.h	28.4 KB	-rw-r--r--	2023-11-28 08:52
fxsrintrin.h	2.82 KB	-rw-r--r--	2023-11-28 08:52
gfniintrin.h	7.57 KB	-rw-r--r--	2023-11-28 08:52
hexagon_circ_brev_intrinsics.h	15.59 KB	-rw-r--r--	2023-11-28 08:52
hexagon_protos.h	374.42 KB	-rw-r--r--	2023-11-28 08:52
hexagon_types.h	130.33 KB	-rw-r--r--	2023-11-28 08:52
hresetintrin.h	1.36 KB	-rw-r--r--	2023-11-28 08:52
htmintrin.h	6.14 KB	-rw-r--r--	2023-11-28 08:52
htmxlintrin.h	9.01 KB	-rw-r--r--	2023-11-28 08:52
hvx_hexagon_protos.h	254.26 KB	-rw-r--r--	2023-11-28 08:52
ia32intrin.h	12.72 KB	-rw-r--r--	2023-11-28 08:52
immintrin.h	23.57 KB	-rw-r--r--	2023-11-28 08:52
intrin.h	28.22 KB	-rw-r--r--	2023-11-28 08:52
inttypes.h	2.26 KB	-rw-r--r--	2023-11-28 08:52
invpcidintrin.h	764 B	-rw-r--r--	2023-11-28 08:52
iso646.h	656 B	-rw-r--r--	2023-11-28 08:52
keylockerintrin.h	17.98 KB	-rw-r--r--	2023-11-28 08:52
larchintrin.h	7.8 KB	-rw-r--r--	2023-11-28 08:52
limits.h	3.61 KB	-rw-r--r--	2023-11-28 08:52
lwpintrin.h	5 KB	-rw-r--r--	2023-11-28 08:52
lzcntintrin.h	3.18 KB	-rw-r--r--	2023-11-28 08:52
mm3dnow.h	4.5 KB	-rw-r--r--	2023-11-28 08:52
mm_malloc.h	1.88 KB	-rw-r--r--	2023-11-28 08:52
mmintrin.h	55.98 KB	-rw-r--r--	2023-11-28 08:52
module.modulemap	3.33 KB	-rw-r--r--	2023-11-28 08:52
movdirintrin.h	1.57 KB	-rw-r--r--	2023-11-28 08:52
msa.h	25.01 KB	-rw-r--r--	2023-11-28 08:52
mwaitxintrin.h	2.19 KB	-rw-r--r--	2023-11-28 08:52
nmmintrin.h	709 B	-rw-r--r--	2023-11-28 08:52
opencl-c-base.h	30.38 KB	-rw-r--r--	2023-11-28 08:52
opencl-c.h	874.39 KB	-rw-r--r--	2023-11-28 08:52
pconfigintrin.h	1.19 KB	-rw-r--r--	2023-11-28 08:52
pkuintrin.h	934 B	-rw-r--r--	2023-11-28 08:52
pmmintrin.h	10.5 KB	-rw-r--r--	2023-11-28 08:52
popcntintrin.h	1.82 KB	-rw-r--r--	2023-11-28 08:52
prfchiintrin.h	2.02 KB	-rw-r--r--	2023-11-28 08:52
prfchwintrin.h	2.06 KB	-rw-r--r--	2023-11-28 08:52
ptwriteintrin.h	1.05 KB	-rw-r--r--	2023-11-28 08:52
raointintrin.h	6.59 KB	-rw-r--r--	2023-11-28 08:52
rdpruintrin.h	1.59 KB	-rw-r--r--	2023-11-28 08:52
rdseedintrin.h	2.85 KB	-rw-r--r--	2023-11-28 08:52
riscv_ntlh.h	855 B	-rw-r--r--	2023-11-28 08:52
rtmintrin.h	1.25 KB	-rw-r--r--	2023-11-28 08:52
s390intrin.h	604 B	-rw-r--r--	2023-11-28 08:52
serializeintrin.h	881 B	-rw-r--r--	2023-11-28 08:52
sgxintrin.h	1.77 KB	-rw-r--r--	2023-11-28 08:52
sha512intrin.h	5.95 KB	-rw-r--r--	2023-11-28 08:52
shaintrin.h	7.37 KB	-rw-r--r--	2023-11-28 08:52
sifive_vector.h	522 B	-rw-r--r--	2023-11-28 08:52
sm3intrin.h	7.29 KB	-rw-r--r--	2023-11-28 08:52
sm4intrin.h	8.2 KB	-rw-r--r--	2023-11-28 08:52
smmintrin.h	99.32 KB	-rw-r--r--	2023-11-28 08:52
stdalign.h	911 B	-rw-r--r--	2023-11-28 08:52
stdarg.h	1.66 KB	-rw-r--r--	2023-11-28 08:52
stdatomic.h	8.3 KB	-rw-r--r--	2023-11-28 08:52
stdbool.h	1.04 KB	-rw-r--r--	2023-11-28 08:52
stddef.h	4.16 KB	-rw-r--r--	2023-11-28 08:52
stdint.h	32.49 KB	-rw-r--r--	2023-11-28 08:52
stdnoreturn.h	1.17 KB	-rw-r--r--	2023-11-28 08:52
tbmintrin.h	3.15 KB	-rw-r--r--	2023-11-28 08:52
tgmath.h	29.68 KB	-rw-r--r--	2023-11-28 08:52
tmmintrin.h	29.51 KB	-rw-r--r--	2023-11-28 08:52
tsxldtrkintrin.h	1.97 KB	-rw-r--r--	2023-11-28 08:52
uintrintrin.h	4.96 KB	-rw-r--r--	2023-11-28 08:52
unwind.h	11.21 KB	-rw-r--r--	2023-11-28 08:52
vadefs.h	1.39 KB	-rw-r--r--	2023-11-28 08:52
vaesintrin.h	2.46 KB	-rw-r--r--	2023-11-28 08:52
varargs.h	477 B	-rw-r--r--	2023-11-28 08:52
vecintrin.h	360.82 KB	-rw-r--r--	2023-11-28 08:52
velintrin.h	2.1 KB	-rw-r--r--	2023-11-28 08:52
velintrin_approx.h	3.54 KB	-rw-r--r--	2023-11-28 08:52
velintrin_gen.h	69.06 KB	-rw-r--r--	2023-11-28 08:52
vpclmulqdqintrin.h	1.06 KB	-rw-r--r--	2023-11-28 08:52
waitpkgintrin.h	1.33 KB	-rw-r--r--	2023-11-28 08:52
wasm_simd128.h	76.25 KB	-rw-r--r--	2023-11-28 08:52
wbnoinvdintrin.h	749 B	-rw-r--r--	2023-11-28 08:52
wmmintrin.h	659 B	-rw-r--r--	2023-11-28 08:52
x86gprintrin.h	2.32 KB	-rw-r--r--	2023-11-28 08:52
x86intrin.h	1.81 KB	-rw-r--r--	2023-11-28 08:52
xmmintrin.h	106.73 KB	-rw-r--r--	2023-11-28 08:52
xopintrin.h	19.96 KB	-rw-r--r--	2023-11-28 08:52
xsavecintrin.h	2.51 KB	-rw-r--r--	2023-11-28 08:52
xsaveintrin.h	1.64 KB	-rw-r--r--	2023-11-28 08:52
xsaveoptintrin.h	1 KB	-rw-r--r--	2023-11-28 08:52
xsavesintrin.h	1.24 KB	-rw-r--r--	2023-11-28 08:52
xtestintrin.h	873 B	-rw-r--r--	2023-11-28 08:52

Rename

/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
 *
 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 * See https://llvm.org/LICENSE.txt for license information.
 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 *
 *===-----------------------------------------------------------------------===
 */

#ifndef __IMMINTRIN_H
#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
#endif // __IMMINTRIN_H

#ifndef __SM3INTRIN_H
#define __SM3INTRIN_H

#define __DEFAULT_FN_ATTRS128                                                  \
  __attribute__((__always_inline__, __nodebug__, __target__("sm3"),            \
                 __min_vector_width__(128)))

/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
///    intrinsic performs an initial calculation for the next four SM3 message
///    words. The calculated results are stored in \a dst.
///
/// \headerfile <immintrin.h>
///
/// \code
/// __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)
/// \endcode
///
/// This intrinsic corresponds to the \c VSM3MSG1 instruction.
///
/// \param __A
///    A 128-bit vector of [4 x int].
/// \param __B
///    A 128-bit vector of [4 x int].
/// \param __C
///    A 128-bit vector of [4 x int].
/// \returns
///    A 128-bit vector of [4 x int].
///
/// \code{.operation}
/// DEFINE ROL32(dword, n) {
/// 	count := n % 32
/// 	dest := (dword << count) | (dword >> (32 - count))
/// 	RETURN dest
/// }
/// DEFINE P1(x) {
/// 	RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
/// }
/// W[0] := __C.dword[0]
/// W[1] := __C.dword[1]
/// W[2] := __C.dword[2]
/// W[3] := __C.dword[3]
/// W[7] := __A.dword[0]
/// W[8] := __A.dword[1]
/// W[9] := __A.dword[2]
/// W[10] := __A.dword[3]
/// W[13] := __B.dword[0]
/// W[14] := __B.dword[1]
/// W[15] := __B.dword[2]
/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
/// TMP3 := W[10] ^ W[3]
/// dst.dword[0] := P1(TMP0)
/// dst.dword[1] := P1(TMP1)
/// dst.dword[2] := P1(TMP2)
/// dst.dword[3] := P1(TMP3)
/// dst[MAX:128] := 0
/// \endcode
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
                                                                  __m128i __B,
                                                                  __m128i __C) {
  return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
                                          (__v4su)__C);
}

/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
///    intrinsic performs the final calculation for the next four SM3 message
///    words. The calculated results are stored in \a dst.
///
/// \headerfile <immintrin.h>
///
/// \code
/// __m128i _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C)
/// \endcode
///
/// This intrinsic corresponds to the \c VSM3MSG2 instruction.
///
/// \param __A
///    A 128-bit vector of [4 x int].
/// \param __B
///    A 128-bit vector of [4 x int].
/// \param __C
///    A 128-bit vector of [4 x int].
/// \returns
///    A 128-bit vector of [4 x int].
///
/// \code{.operation}
/// DEFINE ROL32(dword, n) {
/// 	count := n % 32
/// 	dest := (dword << count) | (dword >> (32-count))
/// 	RETURN dest
/// }
/// WTMP[0] := __A.dword[0]
/// WTMP[1] := __A.dword[1]
/// WTMP[2] := __A.dword[2]
/// WTMP[3] := __A.dword[3]
/// W[3] := __B.dword[0]
/// W[4] := __B.dword[1]
/// W[5] := __B.dword[2]
/// W[6] := __B.dword[3]
/// W[10] := __C.dword[0]
/// W[11] := __C.dword[1]
/// W[12] := __C.dword[2]
/// W[13] := __C.dword[3]
/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
/// dst.dword[0] := W[16]
/// dst.dword[1] := W[17]
/// dst.dword[2] := W[18]
/// dst.dword[3] := W[19]
/// dst[MAX:128] := 0
/// \endcode
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
                                                                  __m128i __B,
                                                                  __m128i __C) {
  return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
                                          (__v4su)__C);
}

/// This intrinsic performs two rounds of SM3 operation using initial SM3 state
///    (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F)
///    from \a __B and a pre-computed words from the \a __C. \a __A with
///    initial SM3 state of (C, D, G, H) assumes input of non-rotated left
///    variables from previous state. The updated SM3 state (A, B, E, F) is
///    written to \a __A. The \a imm8 should contain the even round number
///    for the first of the two rounds computed by this instruction. The
///    computation masks the \a imm8 value by AND’ing it with 0x3E so that only
///    even round numbers from 0 through 62 are used for this operation. The
///    calculated results are stored in \a dst.
///
/// \headerfile <immintrin.h>
///
/// \code
/// __m128i _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int
/// imm8) \endcode
///
/// This intrinsic corresponds to the \c VSM3RNDS2 instruction.
///
/// \param __A
///    A 128-bit vector of [4 x int].
/// \param __B
///    A 128-bit vector of [4 x int].
/// \param __C
///    A 128-bit vector of [4 x int].
/// \param imm8
///    A 8-bit constant integer.
/// \returns
///    A 128-bit vector of [4 x int].
///
/// \code{.operation}
/// DEFINE ROL32(dword, n) {
/// 	count := n % 32
/// 	dest := (dword << count) | (dword >> (32-count))
/// 	RETURN dest
/// }
/// DEFINE P0(dword) {
/// 	RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
/// }
/// DEFINE FF(x,y,z, round){
/// 	IF round < 16
/// 		RETURN (x ^ y ^ z)
/// 	ELSE
/// 		RETURN (x & y) | (x & z) | (y & z)
/// 	FI
/// }
/// DEFINE GG(x, y, z, round){
///   IF round < 16
///   	RETURN (x ^ y ^ z)
///   ELSE
///   	RETURN (x & y) | (~x & z)
///   FI
/// }
/// A[0] := __B.dword[3]
/// B[0] := __B.dword[2]
/// C[0] := __A.dword[3]
/// D[0] := __A.dword[2]
/// E[0] := __B.dword[1]
/// F[0] := __B.dword[0]
/// G[0] := __A.dword[1]
/// H[0] := __A.dword[0]
/// W[0] := __C.dword[0]
/// W[1] := __C.dword[1]
/// W[4] := __C.dword[2]
/// W[5] := __C.dword[3]
/// C[0] := ROL32(C[0], 9)
/// D[0] := ROL32(D[0], 9)
/// G[0] := ROL32(G[0], 19)
/// H[0] := ROL32(H[0], 19)
/// ROUND := __D & 0x3E
/// IF ROUND < 16
/// 	CONST := 0x79CC4519
/// ELSE
/// 	CONST := 0x7A879D8A
/// FI
/// CONST := ROL32(CONST,ROUND)
/// FOR i:= 0 to 1
/// 	S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
/// 	S2 := S1 ^ ROL32(A[i], 12)
/// 	T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4])
/// 	T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
/// 	D[i+1] := C[i]
/// 	C[i+1] := ROL32(B[i],9)
/// 	B[i+1] := A[i]
/// 	A[i+1] := T1
/// 	H[i+1] := G[i]
/// 	G[i+1] := ROL32(F[i], 19)
/// 	F[i+1] := E[i]
/// 	E[i+1] := P0(T2)
/// 	CONST := ROL32(CONST, 1)
/// ENDFOR
/// dst.dword[3] := A[2]
/// dst.dword[2] := B[2]
/// dst.dword[1] := E[2]
/// dst.dword[0] := F[2]
/// dst[MAX:128] := 0
/// \endcode
#define _mm_sm3rnds2_epi32(A, B, C, D)                                         \
  (__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)

#undef __DEFAULT_FN_ATTRS128

#endif // __SM3INTRIN_H