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cuda_wrappers
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2025-06-02 12:56
llvm_libc_wrappers
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2025-06-02 12:56
openmp_wrappers
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2025-06-02 12:56
ppc_wrappers
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2025-06-02 12:56
__clang_cuda_builtin_vars.h
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__clang_cuda_cmath.h
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__clang_cuda_complex_builtins.h
9.36
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__clang_cuda_device_functions.h
56.68
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__clang_cuda_intrinsics.h
29.93
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__clang_cuda_libdevice_declares.h
21.87
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__clang_cuda_math.h
15.99
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__clang_cuda_math_forward_declares.h
8.27
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__clang_cuda_runtime_wrapper.h
17.61
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__clang_cuda_texture_intrinsics.h
31.86
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__clang_hip_cmath.h
26.34
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__clang_hip_libdevice_declares.h
19.87
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__clang_hip_math.h
31.96
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__clang_hip_runtime_wrapper.h
4.65
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__clang_hip_stdlib.h
1.19
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__stddef_max_align_t.h
857
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__wmmintrin_aes.h
5.15
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__wmmintrin_pclmul.h
1.99
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adxintrin.h
7.37
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altivec.h
697.32
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ammintrin.h
7.54
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amxcomplexintrin.h
6.81
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amxfp16intrin.h
1.82
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amxintrin.h
21.12
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arm64intr.h
993
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arm_acle.h
25.66
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arm_bf16.h
548
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arm_cde.h
32.67
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arm_cmse.h
6.21
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arm_fp16.h
16.92
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arm_mve.h
1.48
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arm_neon.h
2.45
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arm_neon_sve_bridge.h
9.48
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arm_sme_draft_spec_subject_to_change.h
60.2
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arm_sve.h
1.51
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armintr.h
843
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avx2intrin.h
186.96
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avx512bf16intrin.h
10.51
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avx512bitalgintrin.h
2.41
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avx512bwintrin.h
75.33
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avx512cdintrin.h
4.12
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avx512dqintrin.h
58.75
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avx512erintrin.h
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avx512fintrin.h
382.64
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avx512fp16intrin.h
156.63
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avx512ifmaintrin.h
2.49
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avx512ifmavlintrin.h
4.31
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avx512pfintrin.h
4.53
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avx512vbmi2intrin.h
13.17
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avx512vbmiintrin.h
3.72
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avx512vbmivlintrin.h
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avx512vlbf16intrin.h
19.21
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avx512vlbitalgintrin.h
4.23
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avx512vlbwintrin.h
121.26
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avx512vlcdintrin.h
7.66
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avx512vldqintrin.h
46.41
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avx512vlfp16intrin.h
85.51
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avx512vlintrin.h
322.29
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avx512vlvbmi2intrin.h
25.72
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avx512vlvnniintrin.h
13.13
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avx512vlvp2intersectintrin.h
4.44
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avx512vnniintrin.h
4.21
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avx512vp2intersectintrin.h
2.9
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avx512vpopcntdqintrin.h
2
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avx512vpopcntdqvlintrin.h
3.31
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avxifmaintrin.h
5.75
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avxintrin.h
195.41
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avxneconvertintrin.h
14.09
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avxvnniint16intrin.h
17.41
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avxvnniint8intrin.h
18.67
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avxvnniintrin.h
10.44
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bmi2intrin.h
7.09
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bmiintrin.h
14.12
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builtins.h
741
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cet.h
1.49
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cetintrin.h
3.27
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cldemoteintrin.h
1.18
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clflushoptintrin.h
1.17
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clwbintrin.h
1.2
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clzerointrin.h
1.19
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cmpccxaddintrin.h
2.33
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cpuid.h
11.01
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crc32intrin.h
3.27
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emmintrin.h
192.64
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enqcmdintrin.h
2.12
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f16cintrin.h
5.39
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float.h
5.63
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fma4intrin.h
6.82
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fmaintrin.h
28.4
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fxsrintrin.h
2.82
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gfniintrin.h
7.57
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hexagon_circ_brev_intrinsics.h
15.59
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hexagon_protos.h
374.42
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hexagon_types.h
130.33
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hresetintrin.h
1.36
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htmintrin.h
6.14
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htmxlintrin.h
9.01
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hvx_hexagon_protos.h
254.26
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ia32intrin.h
12.72
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immintrin.h
23.57
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intrin.h
28.22
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inttypes.h
2.26
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invpcidintrin.h
764
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iso646.h
656
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keylockerintrin.h
17.98
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larchintrin.h
7.8
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limits.h
3.61
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lwpintrin.h
5
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lzcntintrin.h
3.18
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mm3dnow.h
4.5
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mm_malloc.h
1.88
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mmintrin.h
55.98
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module.modulemap
3.33
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movdirintrin.h
1.57
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msa.h
25.01
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mwaitxintrin.h
2.19
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nmmintrin.h
709
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opencl-c-base.h
30.38
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opencl-c.h
874.39
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pconfigintrin.h
1.19
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pkuintrin.h
934
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pmmintrin.h
10.5
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popcntintrin.h
1.82
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prfchiintrin.h
2.02
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prfchwintrin.h
2.06
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ptwriteintrin.h
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raointintrin.h
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rdpruintrin.h
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rdseedintrin.h
2.85
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riscv_ntlh.h
855
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rtmintrin.h
1.25
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s390intrin.h
604
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serializeintrin.h
881
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sgxintrin.h
1.77
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sha512intrin.h
5.95
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shaintrin.h
7.37
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sifive_vector.h
522
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sm3intrin.h
7.29
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sm4intrin.h
8.2
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smmintrin.h
99.32
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stdalign.h
911
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stdarg.h
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stdatomic.h
8.3
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stdbool.h
1.04
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stddef.h
4.16
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stdint.h
32.49
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stdnoreturn.h
1.17
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tbmintrin.h
3.15
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tgmath.h
29.68
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tmmintrin.h
29.51
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tsxldtrkintrin.h
1.97
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uintrintrin.h
4.96
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unwind.h
11.21
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vadefs.h
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vaesintrin.h
2.46
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varargs.h
477
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vecintrin.h
360.82
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velintrin.h
2.1
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velintrin_approx.h
3.54
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velintrin_gen.h
69.06
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vpclmulqdqintrin.h
1.06
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waitpkgintrin.h
1.33
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wasm_simd128.h
76.25
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wbnoinvdintrin.h
749
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wmmintrin.h
659
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x86gprintrin.h
2.32
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x86intrin.h
1.81
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xmmintrin.h
106.73
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xopintrin.h
19.96
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xsavecintrin.h
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xsaveintrin.h
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xsaveoptintrin.h
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xsavesintrin.h
1.24
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xtestintrin.h
873
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Save
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/*===--------------- sm4intrin.h - SM4 intrinsics -----------------=== * * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. * See https://llvm.org/LICENSE.txt for license information. * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception * *===-----------------------------------------------------------------------=== */ #ifndef __IMMINTRIN_H #error "Never use <sm4intrin.h> directly; include <immintrin.h> instead." #endif // __IMMINTRIN_H #ifndef __SM4INTRIN_H #define __SM4INTRIN_H /// This intrinsic performs four rounds of SM4 key expansion. The intrinsic /// operates on independent 128-bit lanes. The calculated results are /// stored in \a dst. /// \headerfile <immintrin.h> /// /// \code /// __m128i _mm_sm4key4_epi32(__m128i __A, __m128i __B) /// \endcode /// /// This intrinsic corresponds to the \c VSM4KEY4 instruction. /// /// \param __A /// A 128-bit vector of [4 x int]. /// \param __B /// A 128-bit vector of [4 x int]. /// \returns /// A 128-bit vector of [4 x int]. /// /// \code{.operation} /// DEFINE ROL32(dword, n) { /// count := n % 32 /// dest := (dword << count) | (dword >> (32-count)) /// RETURN dest /// } /// DEFINE SBOX_BYTE(dword, i) { /// RETURN sbox[dword.byte[i]] /// } /// DEFINE lower_t(dword) { /// tmp.byte[0] := SBOX_BYTE(dword, 0) /// tmp.byte[1] := SBOX_BYTE(dword, 1) /// tmp.byte[2] := SBOX_BYTE(dword, 2) /// tmp.byte[3] := SBOX_BYTE(dword, 3) /// RETURN tmp /// } /// DEFINE L_KEY(dword) { /// RETURN dword ^ ROL32(dword, 13) ^ ROL32(dword, 23) /// } /// DEFINE T_KEY(dword) { /// RETURN L_KEY(lower_t(dword)) /// } /// DEFINE F_KEY(X0, X1, X2, X3, round_key) { /// RETURN X0 ^ T_KEY(X1 ^ X2 ^ X3 ^ round_key) /// } /// FOR i:= 0 to 0 /// P[0] := __B.xmm[i].dword[0] /// P[1] := __B.xmm[i].dword[1] /// P[2] := __B.xmm[i].dword[2] /// P[3] := __B.xmm[i].dword[3] /// C[0] := F_KEY(P[0], P[1], P[2], P[3], __A.xmm[i].dword[0]) /// C[1] := F_KEY(P[1], P[2], P[3], C[0], __A.xmm[i].dword[1]) /// C[2] := F_KEY(P[2], P[3], C[0], C[1], __A.xmm[i].dword[2]) /// C[3] := F_KEY(P[3], C[0], C[1], C[2], __A.xmm[i].dword[3]) /// DEST.xmm[i].dword[0] := C[0] /// DEST.xmm[i].dword[1] := C[1] /// DEST.xmm[i].dword[2] := C[2] /// DEST.xmm[i].dword[3] := C[3] /// ENDFOR /// DEST[MAX:128] := 0 /// \endcode #define _mm_sm4key4_epi32(A, B) \ (__m128i) __builtin_ia32_vsm4key4128((__v4su)A, (__v4su)B) /// This intrinsic performs four rounds of SM4 key expansion. The intrinsic /// operates on independent 128-bit lanes. The calculated results are /// stored in \a dst. /// \headerfile <immintrin.h> /// /// \code /// __m256i _mm256_sm4key4_epi32(__m256i __A, __m256i __B) /// \endcode /// /// This intrinsic corresponds to the \c VSM4KEY4 instruction. /// /// \param __A /// A 256-bit vector of [8 x int]. /// \param __B /// A 256-bit vector of [8 x int]. /// \returns /// A 256-bit vector of [8 x int]. /// /// \code{.operation} /// DEFINE ROL32(dword, n) { /// count := n % 32 /// dest := (dword << count) | (dword >> (32-count)) /// RETURN dest /// } /// DEFINE SBOX_BYTE(dword, i) { /// RETURN sbox[dword.byte[i]] /// } /// DEFINE lower_t(dword) { /// tmp.byte[0] := SBOX_BYTE(dword, 0) /// tmp.byte[1] := SBOX_BYTE(dword, 1) /// tmp.byte[2] := SBOX_BYTE(dword, 2) /// tmp.byte[3] := SBOX_BYTE(dword, 3) /// RETURN tmp /// } /// DEFINE L_KEY(dword) { /// RETURN dword ^ ROL32(dword, 13) ^ ROL32(dword, 23) /// } /// DEFINE T_KEY(dword) { /// RETURN L_KEY(lower_t(dword)) /// } /// DEFINE F_KEY(X0, X1, X2, X3, round_key) { /// RETURN X0 ^ T_KEY(X1 ^ X2 ^ X3 ^ round_key) /// } /// FOR i:= 0 to 1 /// P[0] := __B.xmm[i].dword[0] /// P[1] := __B.xmm[i].dword[1] /// P[2] := __B.xmm[i].dword[2] /// P[3] := __B.xmm[i].dword[3] /// C[0] := F_KEY(P[0], P[1], P[2], P[3], __A.xmm[i].dword[0]) /// C[1] := F_KEY(P[1], P[2], P[3], C[0], __A.xmm[i].dword[1]) /// C[2] := F_KEY(P[2], P[3], C[0], C[1], __A.xmm[i].dword[2]) /// C[3] := F_KEY(P[3], C[0], C[1], C[2], __A.xmm[i].dword[3]) /// DEST.xmm[i].dword[0] := C[0] /// DEST.xmm[i].dword[1] := C[1] /// DEST.xmm[i].dword[2] := C[2] /// DEST.xmm[i].dword[3] := C[3] /// ENDFOR /// DEST[MAX:256] := 0 /// \endcode #define _mm256_sm4key4_epi32(A, B) \ (__m256i) __builtin_ia32_vsm4key4256((__v8su)A, (__v8su)B) /// This intrinisc performs four rounds of SM4 encryption. The intrinisc /// operates on independent 128-bit lanes. The calculated results are /// stored in \a dst. /// \headerfile <immintrin.h> /// /// \code /// __m128i _mm_sm4rnds4_epi32(__m128i __A, __m128i __B) /// \endcode /// /// This intrinsic corresponds to the \c VSM4RNDS4 instruction. /// /// \param __A /// A 128-bit vector of [4 x int]. /// \param __B /// A 128-bit vector of [4 x int]. /// \returns /// A 128-bit vector of [4 x int]. /// /// \code{.operation} /// DEFINE ROL32(dword, n) { /// count := n % 32 /// dest := (dword << count) | (dword >> (32-count)) /// RETURN dest /// } /// DEFINE lower_t(dword) { /// tmp.byte[0] := SBOX_BYTE(dword, 0) /// tmp.byte[1] := SBOX_BYTE(dword, 1) /// tmp.byte[2] := SBOX_BYTE(dword, 2) /// tmp.byte[3] := SBOX_BYTE(dword, 3) /// RETURN tmp /// } /// DEFINE L_RND(dword) { /// tmp := dword /// tmp := tmp ^ ROL32(dword, 2) /// tmp := tmp ^ ROL32(dword, 10) /// tmp := tmp ^ ROL32(dword, 18) /// tmp := tmp ^ ROL32(dword, 24) /// RETURN tmp /// } /// DEFINE T_RND(dword) { /// RETURN L_RND(lower_t(dword)) /// } /// DEFINE F_RND(X0, X1, X2, X3, round_key) { /// RETURN X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key) /// } /// FOR i:= 0 to 0 /// P[0] := __B.xmm[i].dword[0] /// P[1] := __B.xmm[i].dword[1] /// P[2] := __B.xmm[i].dword[2] /// P[3] := __B.xmm[i].dword[3] /// C[0] := F_RND(P[0], P[1], P[2], P[3], __A.xmm[i].dword[0]) /// C[1] := F_RND(P[1], P[2], P[3], C[0], __A.xmm[i].dword[1]) /// C[2] := F_RND(P[2], P[3], C[0], C[1], __A.xmm[i].dword[2]) /// C[3] := F_RND(P[3], C[0], C[1], C[2], __A.xmm[i].dword[3]) /// DEST.xmm[i].dword[0] := C[0] /// DEST.xmm[i].dword[1] := C[1] /// DEST.xmm[i].dword[2] := C[2] /// DEST.xmm[i].dword[3] := C[3] /// ENDFOR /// DEST[MAX:128] := 0 /// \endcode #define _mm_sm4rnds4_epi32(A, B) \ (__m128i) __builtin_ia32_vsm4rnds4128((__v4su)A, (__v4su)B) /// This intrinisc performs four rounds of SM4 encryption. The intrinisc /// operates on independent 128-bit lanes. The calculated results are /// stored in \a dst. /// \headerfile <immintrin.h> /// /// \code /// __m256i _mm256_sm4rnds4_epi32(__m256i __A, __m256i __B) /// \endcode /// /// This intrinsic corresponds to the \c VSM4RNDS4 instruction. /// /// \param __A /// A 256-bit vector of [8 x int]. /// \param __B /// A 256-bit vector of [8 x int]. /// \returns /// A 256-bit vector of [8 x int]. /// /// \code{.operation} /// DEFINE ROL32(dword, n) { /// count := n % 32 /// dest := (dword << count) | (dword >> (32-count)) /// RETURN dest /// } /// DEFINE lower_t(dword) { /// tmp.byte[0] := SBOX_BYTE(dword, 0) /// tmp.byte[1] := SBOX_BYTE(dword, 1) /// tmp.byte[2] := SBOX_BYTE(dword, 2) /// tmp.byte[3] := SBOX_BYTE(dword, 3) /// RETURN tmp /// } /// DEFINE L_RND(dword) { /// tmp := dword /// tmp := tmp ^ ROL32(dword, 2) /// tmp := tmp ^ ROL32(dword, 10) /// tmp := tmp ^ ROL32(dword, 18) /// tmp := tmp ^ ROL32(dword, 24) /// RETURN tmp /// } /// DEFINE T_RND(dword) { /// RETURN L_RND(lower_t(dword)) /// } /// DEFINE F_RND(X0, X1, X2, X3, round_key) { /// RETURN X0 ^ T_RND(X1 ^ X2 ^ X3 ^ round_key) /// } /// FOR i:= 0 to 0 /// P[0] := __B.xmm[i].dword[0] /// P[1] := __B.xmm[i].dword[1] /// P[2] := __B.xmm[i].dword[2] /// P[3] := __B.xmm[i].dword[3] /// C[0] := F_RND(P[0], P[1], P[2], P[3], __A.xmm[i].dword[0]) /// C[1] := F_RND(P[1], P[2], P[3], C[0], __A.xmm[i].dword[1]) /// C[2] := F_RND(P[2], P[3], C[0], C[1], __A.xmm[i].dword[2]) /// C[3] := F_RND(P[3], C[0], C[1], C[2], __A.xmm[i].dword[3]) /// DEST.xmm[i].dword[0] := C[0] /// DEST.xmm[i].dword[1] := C[1] /// DEST.xmm[i].dword[2] := C[2] /// DEST.xmm[i].dword[3] := C[3] /// ENDFOR /// DEST[MAX:256] := 0 /// \endcode #define _mm256_sm4rnds4_epi32(A, B) \ (__m256i) __builtin_ia32_vsm4rnds4256((__v8su)A, (__v8su)B) #endif // __SM4INTRIN_H