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cuda_wrappers
[ DIR ]
drwxr-xr-x
2025-06-02 12:56
llvm_libc_wrappers
[ DIR ]
drwxr-xr-x
2025-06-02 12:56
openmp_wrappers
[ DIR ]
drwxr-xr-x
2025-06-02 12:56
ppc_wrappers
[ DIR ]
drwxr-xr-x
2025-06-02 12:56
__clang_cuda_builtin_vars.h
4.78
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2023-11-28 08:52
__clang_cuda_cmath.h
18.06
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__clang_cuda_complex_builtins.h
9.36
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__clang_cuda_device_functions.h
56.68
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__clang_cuda_intrinsics.h
29.93
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__clang_cuda_libdevice_declares.h
21.87
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__clang_cuda_math.h
15.99
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__clang_cuda_math_forward_declares.h
8.27
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__clang_cuda_runtime_wrapper.h
17.61
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__clang_cuda_texture_intrinsics.h
31.86
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__clang_hip_cmath.h
26.34
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2023-11-28 08:52
__clang_hip_libdevice_declares.h
19.87
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__clang_hip_math.h
31.96
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__clang_hip_runtime_wrapper.h
4.65
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__clang_hip_stdlib.h
1.19
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__stddef_max_align_t.h
857
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__wmmintrin_aes.h
5.15
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__wmmintrin_pclmul.h
1.99
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adxintrin.h
7.37
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2023-11-28 08:52
altivec.h
697.32
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ammintrin.h
7.54
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amxcomplexintrin.h
6.81
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2023-11-28 08:52
amxfp16intrin.h
1.82
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amxintrin.h
21.12
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arm64intr.h
993
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arm_acle.h
25.66
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arm_bf16.h
548
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2024-11-06 08:03
arm_cde.h
32.67
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2024-11-06 08:03
arm_cmse.h
6.21
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arm_fp16.h
16.92
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2024-11-06 08:03
arm_mve.h
1.48
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arm_neon.h
2.45
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arm_neon_sve_bridge.h
9.48
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arm_sme_draft_spec_subject_to_change.h
60.2
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2024-11-06 08:03
arm_sve.h
1.51
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armintr.h
843
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avx2intrin.h
186.96
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avx512bf16intrin.h
10.51
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avx512bitalgintrin.h
2.41
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avx512bwintrin.h
75.33
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avx512cdintrin.h
4.12
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avx512dqintrin.h
58.75
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avx512erintrin.h
11.83
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avx512fintrin.h
382.64
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avx512fp16intrin.h
156.63
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avx512ifmaintrin.h
2.49
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avx512ifmavlintrin.h
4.31
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avx512pfintrin.h
4.53
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avx512vbmi2intrin.h
13.17
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avx512vbmiintrin.h
3.72
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avx512vbmivlintrin.h
6.94
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avx512vlbf16intrin.h
19.21
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avx512vlbitalgintrin.h
4.23
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avx512vlbwintrin.h
121.26
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avx512vlcdintrin.h
7.66
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avx512vldqintrin.h
46.41
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avx512vlfp16intrin.h
85.51
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avx512vlintrin.h
322.29
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avx512vlvbmi2intrin.h
25.72
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avx512vlvnniintrin.h
13.13
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avx512vlvp2intersectintrin.h
4.44
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avx512vnniintrin.h
4.21
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avx512vp2intersectintrin.h
2.9
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avx512vpopcntdqintrin.h
2
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avx512vpopcntdqvlintrin.h
3.31
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avxifmaintrin.h
5.75
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avxintrin.h
195.41
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avxneconvertintrin.h
14.09
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avxvnniint16intrin.h
17.41
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avxvnniint8intrin.h
18.67
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avxvnniintrin.h
10.44
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2023-11-28 08:52
bmi2intrin.h
7.09
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2023-11-28 08:52
bmiintrin.h
14.12
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2023-11-28 08:52
builtins.h
741
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cet.h
1.49
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cetintrin.h
3.27
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cldemoteintrin.h
1.18
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clflushoptintrin.h
1.17
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clwbintrin.h
1.2
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clzerointrin.h
1.19
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cmpccxaddintrin.h
2.33
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cpuid.h
11.01
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crc32intrin.h
3.27
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emmintrin.h
192.64
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enqcmdintrin.h
2.12
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f16cintrin.h
5.39
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float.h
5.63
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fma4intrin.h
6.82
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fmaintrin.h
28.4
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fxsrintrin.h
2.82
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gfniintrin.h
7.57
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2023-11-28 08:52
hexagon_circ_brev_intrinsics.h
15.59
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hexagon_protos.h
374.42
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hexagon_types.h
130.33
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hresetintrin.h
1.36
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htmintrin.h
6.14
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htmxlintrin.h
9.01
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hvx_hexagon_protos.h
254.26
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ia32intrin.h
12.72
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immintrin.h
23.57
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intrin.h
28.22
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inttypes.h
2.26
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invpcidintrin.h
764
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iso646.h
656
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keylockerintrin.h
17.98
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larchintrin.h
7.8
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2023-11-28 08:52
limits.h
3.61
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lwpintrin.h
5
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lzcntintrin.h
3.18
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mm3dnow.h
4.5
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mm_malloc.h
1.88
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mmintrin.h
55.98
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module.modulemap
3.33
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movdirintrin.h
1.57
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msa.h
25.01
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mwaitxintrin.h
2.19
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nmmintrin.h
709
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opencl-c-base.h
30.38
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opencl-c.h
874.39
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pconfigintrin.h
1.19
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pkuintrin.h
934
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pmmintrin.h
10.5
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popcntintrin.h
1.82
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prfchiintrin.h
2.02
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prfchwintrin.h
2.06
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ptwriteintrin.h
1.05
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raointintrin.h
6.59
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rdpruintrin.h
1.59
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rdseedintrin.h
2.85
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riscv_ntlh.h
855
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rtmintrin.h
1.25
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s390intrin.h
604
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serializeintrin.h
881
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sgxintrin.h
1.77
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sha512intrin.h
5.95
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shaintrin.h
7.37
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sifive_vector.h
522
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sm3intrin.h
7.29
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sm4intrin.h
8.2
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smmintrin.h
99.32
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stdalign.h
911
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stdarg.h
1.66
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stdatomic.h
8.3
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stdbool.h
1.04
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stddef.h
4.16
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stdint.h
32.49
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stdnoreturn.h
1.17
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tbmintrin.h
3.15
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tgmath.h
29.68
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tmmintrin.h
29.51
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tsxldtrkintrin.h
1.97
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uintrintrin.h
4.96
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unwind.h
11.21
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vadefs.h
1.39
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vaesintrin.h
2.46
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varargs.h
477
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vecintrin.h
360.82
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velintrin.h
2.1
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velintrin_approx.h
3.54
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velintrin_gen.h
69.06
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vpclmulqdqintrin.h
1.06
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waitpkgintrin.h
1.33
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wasm_simd128.h
76.25
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wbnoinvdintrin.h
749
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wmmintrin.h
659
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x86gprintrin.h
2.32
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x86intrin.h
1.81
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xmmintrin.h
106.73
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xopintrin.h
19.96
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xsavecintrin.h
2.51
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xsaveintrin.h
1.64
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xsaveoptintrin.h
1
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xsavesintrin.h
1.24
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xtestintrin.h
873
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Save
Rename
/*===---- mmintrin.h - MMX intrinsics --------------------------------------=== * * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. * See https://llvm.org/LICENSE.txt for license information. * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception * *===-----------------------------------------------------------------------=== */ #ifndef __MMINTRIN_H #define __MMINTRIN_H #if !defined(__i386__) && !defined(__x86_64__) #error "This header is only meant to be used on x86 and x64 architecture" #endif typedef long long __m64 __attribute__((__vector_size__(8), __aligned__(8))); typedef long long __v1di __attribute__((__vector_size__(8))); typedef int __v2si __attribute__((__vector_size__(8))); typedef short __v4hi __attribute__((__vector_size__(8))); typedef char __v8qi __attribute__((__vector_size__(8))); /* Define the default attributes for the functions in this file. */ #define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__, __target__("mmx"), __min_vector_width__(64))) /// Clears the MMX state by setting the state of the x87 stack registers /// to empty. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> EMMS </c> instruction. /// static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("mmx"))) _mm_empty(void) { __builtin_ia32_emms(); } /// Constructs a 64-bit integer vector, setting the lower 32 bits to the /// value of the 32-bit integer parameter and setting the upper 32 bits to 0. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> MOVD </c> instruction. /// /// \param __i /// A 32-bit integer value. /// \returns A 64-bit integer vector. The lower 32 bits contain the value of the /// parameter. The upper 32 bits are set to 0. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cvtsi32_si64(int __i) { return (__m64)__builtin_ia32_vec_init_v2si(__i, 0); } /// Returns the lower 32 bits of a 64-bit integer vector as a 32-bit /// signed integer. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> MOVD </c> instruction. /// /// \param __m /// A 64-bit integer vector. /// \returns A 32-bit signed integer value containing the lower 32 bits of the /// parameter. static __inline__ int __DEFAULT_FN_ATTRS _mm_cvtsi64_si32(__m64 __m) { return __builtin_ia32_vec_ext_v2si((__v2si)__m, 0); } /// Casts a 64-bit signed integer value into a 64-bit integer vector. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> MOVQ </c> instruction. /// /// \param __i /// A 64-bit signed integer. /// \returns A 64-bit integer vector containing the same bitwise pattern as the /// parameter. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cvtsi64_m64(long long __i) { return (__m64)__i; } /// Casts a 64-bit integer vector into a 64-bit signed integer value. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> MOVQ </c> instruction. /// /// \param __m /// A 64-bit integer vector. /// \returns A 64-bit signed integer containing the same bitwise pattern as the /// parameter. static __inline__ long long __DEFAULT_FN_ATTRS _mm_cvtm64_si64(__m64 __m) { return (long long)__m; } /// Converts 16-bit signed integers from both 64-bit integer vector /// parameters of [4 x i16] into 8-bit signed integer values, and constructs /// a 64-bit integer vector of [8 x i8] as the result. Positive values /// greater than 0x7F are saturated to 0x7F. Negative values less than 0x80 /// are saturated to 0x80. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PACKSSWB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. Each 16-bit element is treated as a /// 16-bit signed integer and is converted to an 8-bit signed integer with /// saturation. Positive values greater than 0x7F are saturated to 0x7F. /// Negative values less than 0x80 are saturated to 0x80. The converted /// [4 x i8] values are written to the lower 32 bits of the result. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. Each 16-bit element is treated as a /// 16-bit signed integer and is converted to an 8-bit signed integer with /// saturation. Positive values greater than 0x7F are saturated to 0x7F. /// Negative values less than 0x80 are saturated to 0x80. The converted /// [4 x i8] values are written to the upper 32 bits of the result. /// \returns A 64-bit integer vector of [8 x i8] containing the converted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_packs_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_packsswb((__v4hi)__m1, (__v4hi)__m2); } /// Converts 32-bit signed integers from both 64-bit integer vector /// parameters of [2 x i32] into 16-bit signed integer values, and constructs /// a 64-bit integer vector of [4 x i16] as the result. Positive values /// greater than 0x7FFF are saturated to 0x7FFF. Negative values less than /// 0x8000 are saturated to 0x8000. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PACKSSDW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [2 x i32]. Each 32-bit element is treated as a /// 32-bit signed integer and is converted to a 16-bit signed integer with /// saturation. Positive values greater than 0x7FFF are saturated to 0x7FFF. /// Negative values less than 0x8000 are saturated to 0x8000. The converted /// [2 x i16] values are written to the lower 32 bits of the result. /// \param __m2 /// A 64-bit integer vector of [2 x i32]. Each 32-bit element is treated as a /// 32-bit signed integer and is converted to a 16-bit signed integer with /// saturation. Positive values greater than 0x7FFF are saturated to 0x7FFF. /// Negative values less than 0x8000 are saturated to 0x8000. The converted /// [2 x i16] values are written to the upper 32 bits of the result. /// \returns A 64-bit integer vector of [4 x i16] containing the converted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_packs_pi32(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_packssdw((__v2si)__m1, (__v2si)__m2); } /// Converts 16-bit signed integers from both 64-bit integer vector /// parameters of [4 x i16] into 8-bit unsigned integer values, and /// constructs a 64-bit integer vector of [8 x i8] as the result. Values /// greater than 0xFF are saturated to 0xFF. Values less than 0 are saturated /// to 0. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PACKUSWB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. Each 16-bit element is treated as a /// 16-bit signed integer and is converted to an 8-bit unsigned integer with /// saturation. Values greater than 0xFF are saturated to 0xFF. Values less /// than 0 are saturated to 0. The converted [4 x i8] values are written to /// the lower 32 bits of the result. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. Each 16-bit element is treated as a /// 16-bit signed integer and is converted to an 8-bit unsigned integer with /// saturation. Values greater than 0xFF are saturated to 0xFF. Values less /// than 0 are saturated to 0. The converted [4 x i8] values are written to /// the upper 32 bits of the result. /// \returns A 64-bit integer vector of [8 x i8] containing the converted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_packs_pu16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_packuswb((__v4hi)__m1, (__v4hi)__m2); } /// Unpacks the upper 32 bits from two 64-bit integer vectors of [8 x i8] /// and interleaves them into a 64-bit integer vector of [8 x i8]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PUNPCKHBW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8]. \n /// Bits [39:32] are written to bits [7:0] of the result. \n /// Bits [47:40] are written to bits [23:16] of the result. \n /// Bits [55:48] are written to bits [39:32] of the result. \n /// Bits [63:56] are written to bits [55:48] of the result. /// \param __m2 /// A 64-bit integer vector of [8 x i8]. /// Bits [39:32] are written to bits [15:8] of the result. \n /// Bits [47:40] are written to bits [31:24] of the result. \n /// Bits [55:48] are written to bits [47:40] of the result. \n /// Bits [63:56] are written to bits [63:56] of the result. /// \returns A 64-bit integer vector of [8 x i8] containing the interleaved /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_unpackhi_pi8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_punpckhbw((__v8qi)__m1, (__v8qi)__m2); } /// Unpacks the upper 32 bits from two 64-bit integer vectors of /// [4 x i16] and interleaves them into a 64-bit integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PUNPCKHWD </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// Bits [47:32] are written to bits [15:0] of the result. \n /// Bits [63:48] are written to bits [47:32] of the result. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// Bits [47:32] are written to bits [31:16] of the result. \n /// Bits [63:48] are written to bits [63:48] of the result. /// \returns A 64-bit integer vector of [4 x i16] containing the interleaved /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_unpackhi_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_punpckhwd((__v4hi)__m1, (__v4hi)__m2); } /// Unpacks the upper 32 bits from two 64-bit integer vectors of /// [2 x i32] and interleaves them into a 64-bit integer vector of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PUNPCKHDQ </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [2 x i32]. The upper 32 bits are written to /// the lower 32 bits of the result. /// \param __m2 /// A 64-bit integer vector of [2 x i32]. The upper 32 bits are written to /// the upper 32 bits of the result. /// \returns A 64-bit integer vector of [2 x i32] containing the interleaved /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_unpackhi_pi32(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_punpckhdq((__v2si)__m1, (__v2si)__m2); } /// Unpacks the lower 32 bits from two 64-bit integer vectors of [8 x i8] /// and interleaves them into a 64-bit integer vector of [8 x i8]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PUNPCKLBW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8]. /// Bits [7:0] are written to bits [7:0] of the result. \n /// Bits [15:8] are written to bits [23:16] of the result. \n /// Bits [23:16] are written to bits [39:32] of the result. \n /// Bits [31:24] are written to bits [55:48] of the result. /// \param __m2 /// A 64-bit integer vector of [8 x i8]. /// Bits [7:0] are written to bits [15:8] of the result. \n /// Bits [15:8] are written to bits [31:24] of the result. \n /// Bits [23:16] are written to bits [47:40] of the result. \n /// Bits [31:24] are written to bits [63:56] of the result. /// \returns A 64-bit integer vector of [8 x i8] containing the interleaved /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_unpacklo_pi8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_punpcklbw((__v8qi)__m1, (__v8qi)__m2); } /// Unpacks the lower 32 bits from two 64-bit integer vectors of /// [4 x i16] and interleaves them into a 64-bit integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PUNPCKLWD </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// Bits [15:0] are written to bits [15:0] of the result. \n /// Bits [31:16] are written to bits [47:32] of the result. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// Bits [15:0] are written to bits [31:16] of the result. \n /// Bits [31:16] are written to bits [63:48] of the result. /// \returns A 64-bit integer vector of [4 x i16] containing the interleaved /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_unpacklo_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_punpcklwd((__v4hi)__m1, (__v4hi)__m2); } /// Unpacks the lower 32 bits from two 64-bit integer vectors of /// [2 x i32] and interleaves them into a 64-bit integer vector of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PUNPCKLDQ </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [2 x i32]. The lower 32 bits are written to /// the lower 32 bits of the result. /// \param __m2 /// A 64-bit integer vector of [2 x i32]. The lower 32 bits are written to /// the upper 32 bits of the result. /// \returns A 64-bit integer vector of [2 x i32] containing the interleaved /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_unpacklo_pi32(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_punpckldq((__v2si)__m1, (__v2si)__m2); } /// Adds each 8-bit integer element of the first 64-bit integer vector /// of [8 x i8] to the corresponding 8-bit integer element of the second /// 64-bit integer vector of [8 x i8]. The lower 8 bits of the results are /// packed into a 64-bit integer vector of [8 x i8]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PADDB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8]. /// \param __m2 /// A 64-bit integer vector of [8 x i8]. /// \returns A 64-bit integer vector of [8 x i8] containing the sums of both /// parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_add_pi8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_paddb((__v8qi)__m1, (__v8qi)__m2); } /// Adds each 16-bit integer element of the first 64-bit integer vector /// of [4 x i16] to the corresponding 16-bit integer element of the second /// 64-bit integer vector of [4 x i16]. The lower 16 bits of the results are /// packed into a 64-bit integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PADDW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// \returns A 64-bit integer vector of [4 x i16] containing the sums of both /// parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_add_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_paddw((__v4hi)__m1, (__v4hi)__m2); } /// Adds each 32-bit integer element of the first 64-bit integer vector /// of [2 x i32] to the corresponding 32-bit integer element of the second /// 64-bit integer vector of [2 x i32]. The lower 32 bits of the results are /// packed into a 64-bit integer vector of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PADDD </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [2 x i32]. /// \param __m2 /// A 64-bit integer vector of [2 x i32]. /// \returns A 64-bit integer vector of [2 x i32] containing the sums of both /// parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_add_pi32(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_paddd((__v2si)__m1, (__v2si)__m2); } /// Adds each 8-bit signed integer element of the first 64-bit integer /// vector of [8 x i8] to the corresponding 8-bit signed integer element of /// the second 64-bit integer vector of [8 x i8]. Positive sums greater than /// 0x7F are saturated to 0x7F. Negative sums less than 0x80 are saturated to /// 0x80. The results are packed into a 64-bit integer vector of [8 x i8]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PADDSB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8]. /// \param __m2 /// A 64-bit integer vector of [8 x i8]. /// \returns A 64-bit integer vector of [8 x i8] containing the saturated sums /// of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_adds_pi8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_paddsb((__v8qi)__m1, (__v8qi)__m2); } /// Adds each 16-bit signed integer element of the first 64-bit integer /// vector of [4 x i16] to the corresponding 16-bit signed integer element of /// the second 64-bit integer vector of [4 x i16]. Positive sums greater than /// 0x7FFF are saturated to 0x7FFF. Negative sums less than 0x8000 are /// saturated to 0x8000. The results are packed into a 64-bit integer vector /// of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PADDSW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// \returns A 64-bit integer vector of [4 x i16] containing the saturated sums /// of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_adds_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_paddsw((__v4hi)__m1, (__v4hi)__m2); } /// Adds each 8-bit unsigned integer element of the first 64-bit integer /// vector of [8 x i8] to the corresponding 8-bit unsigned integer element of /// the second 64-bit integer vector of [8 x i8]. Sums greater than 0xFF are /// saturated to 0xFF. The results are packed into a 64-bit integer vector of /// [8 x i8]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PADDUSB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8]. /// \param __m2 /// A 64-bit integer vector of [8 x i8]. /// \returns A 64-bit integer vector of [8 x i8] containing the saturated /// unsigned sums of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_adds_pu8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_paddusb((__v8qi)__m1, (__v8qi)__m2); } /// Adds each 16-bit unsigned integer element of the first 64-bit integer /// vector of [4 x i16] to the corresponding 16-bit unsigned integer element /// of the second 64-bit integer vector of [4 x i16]. Sums greater than /// 0xFFFF are saturated to 0xFFFF. The results are packed into a 64-bit /// integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PADDUSW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// \returns A 64-bit integer vector of [4 x i16] containing the saturated /// unsigned sums of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_adds_pu16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_paddusw((__v4hi)__m1, (__v4hi)__m2); } /// Subtracts each 8-bit integer element of the second 64-bit integer /// vector of [8 x i8] from the corresponding 8-bit integer element of the /// first 64-bit integer vector of [8 x i8]. The lower 8 bits of the results /// are packed into a 64-bit integer vector of [8 x i8]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSUBB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8] containing the minuends. /// \param __m2 /// A 64-bit integer vector of [8 x i8] containing the subtrahends. /// \returns A 64-bit integer vector of [8 x i8] containing the differences of /// both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sub_pi8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_psubb((__v8qi)__m1, (__v8qi)__m2); } /// Subtracts each 16-bit integer element of the second 64-bit integer /// vector of [4 x i16] from the corresponding 16-bit integer element of the /// first 64-bit integer vector of [4 x i16]. The lower 16 bits of the /// results are packed into a 64-bit integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSUBW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16] containing the minuends. /// \param __m2 /// A 64-bit integer vector of [4 x i16] containing the subtrahends. /// \returns A 64-bit integer vector of [4 x i16] containing the differences of /// both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sub_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_psubw((__v4hi)__m1, (__v4hi)__m2); } /// Subtracts each 32-bit integer element of the second 64-bit integer /// vector of [2 x i32] from the corresponding 32-bit integer element of the /// first 64-bit integer vector of [2 x i32]. The lower 32 bits of the /// results are packed into a 64-bit integer vector of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSUBD </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [2 x i32] containing the minuends. /// \param __m2 /// A 64-bit integer vector of [2 x i32] containing the subtrahends. /// \returns A 64-bit integer vector of [2 x i32] containing the differences of /// both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sub_pi32(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_psubd((__v2si)__m1, (__v2si)__m2); } /// Subtracts each 8-bit signed integer element of the second 64-bit /// integer vector of [8 x i8] from the corresponding 8-bit signed integer /// element of the first 64-bit integer vector of [8 x i8]. Positive results /// greater than 0x7F are saturated to 0x7F. Negative results less than 0x80 /// are saturated to 0x80. The results are packed into a 64-bit integer /// vector of [8 x i8]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSUBSB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8] containing the minuends. /// \param __m2 /// A 64-bit integer vector of [8 x i8] containing the subtrahends. /// \returns A 64-bit integer vector of [8 x i8] containing the saturated /// differences of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_subs_pi8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_psubsb((__v8qi)__m1, (__v8qi)__m2); } /// Subtracts each 16-bit signed integer element of the second 64-bit /// integer vector of [4 x i16] from the corresponding 16-bit signed integer /// element of the first 64-bit integer vector of [4 x i16]. Positive results /// greater than 0x7FFF are saturated to 0x7FFF. Negative results less than /// 0x8000 are saturated to 0x8000. The results are packed into a 64-bit /// integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSUBSW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16] containing the minuends. /// \param __m2 /// A 64-bit integer vector of [4 x i16] containing the subtrahends. /// \returns A 64-bit integer vector of [4 x i16] containing the saturated /// differences of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_subs_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_psubsw((__v4hi)__m1, (__v4hi)__m2); } /// Subtracts each 8-bit unsigned integer element of the second 64-bit /// integer vector of [8 x i8] from the corresponding 8-bit unsigned integer /// element of the first 64-bit integer vector of [8 x i8]. /// /// If an element of the first vector is less than the corresponding element /// of the second vector, the result is saturated to 0. The results are /// packed into a 64-bit integer vector of [8 x i8]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSUBUSB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8] containing the minuends. /// \param __m2 /// A 64-bit integer vector of [8 x i8] containing the subtrahends. /// \returns A 64-bit integer vector of [8 x i8] containing the saturated /// differences of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_subs_pu8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_psubusb((__v8qi)__m1, (__v8qi)__m2); } /// Subtracts each 16-bit unsigned integer element of the second 64-bit /// integer vector of [4 x i16] from the corresponding 16-bit unsigned /// integer element of the first 64-bit integer vector of [4 x i16]. /// /// If an element of the first vector is less than the corresponding element /// of the second vector, the result is saturated to 0. The results are /// packed into a 64-bit integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSUBUSW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16] containing the minuends. /// \param __m2 /// A 64-bit integer vector of [4 x i16] containing the subtrahends. /// \returns A 64-bit integer vector of [4 x i16] containing the saturated /// differences of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_subs_pu16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_psubusw((__v4hi)__m1, (__v4hi)__m2); } /// Multiplies each 16-bit signed integer element of the first 64-bit /// integer vector of [4 x i16] by the corresponding 16-bit signed integer /// element of the second 64-bit integer vector of [4 x i16] and get four /// 32-bit products. Adds adjacent pairs of products to get two 32-bit sums. /// The lower 32 bits of these two sums are packed into a 64-bit integer /// vector of [2 x i32]. /// /// For example, bits [15:0] of both parameters are multiplied, bits [31:16] /// of both parameters are multiplied, and the sum of both results is written /// to bits [31:0] of the result. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PMADDWD </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// \returns A 64-bit integer vector of [2 x i32] containing the sums of /// products of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_madd_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pmaddwd((__v4hi)__m1, (__v4hi)__m2); } /// Multiplies each 16-bit signed integer element of the first 64-bit /// integer vector of [4 x i16] by the corresponding 16-bit signed integer /// element of the second 64-bit integer vector of [4 x i16]. Packs the upper /// 16 bits of the 32-bit products into a 64-bit integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PMULHW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// \returns A 64-bit integer vector of [4 x i16] containing the upper 16 bits /// of the products of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_mulhi_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pmulhw((__v4hi)__m1, (__v4hi)__m2); } /// Multiplies each 16-bit signed integer element of the first 64-bit /// integer vector of [4 x i16] by the corresponding 16-bit signed integer /// element of the second 64-bit integer vector of [4 x i16]. Packs the lower /// 16 bits of the 32-bit products into a 64-bit integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PMULLW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// \returns A 64-bit integer vector of [4 x i16] containing the lower 16 bits /// of the products of both parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_mullo_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pmullw((__v4hi)__m1, (__v4hi)__m2); } /// Left-shifts each 16-bit signed integer element of the first /// parameter, which is a 64-bit integer vector of [4 x i16], by the number /// of bits specified by the second parameter, which is a 64-bit integer. The /// lower 16 bits of the results are packed into a 64-bit integer vector of /// [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSLLW </c> instruction. /// /// \param __m /// A 64-bit integer vector of [4 x i16]. /// \param __count /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \returns A 64-bit integer vector of [4 x i16] containing the left-shifted /// values. If \a __count is greater or equal to 16, the result is set to all /// 0. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sll_pi16(__m64 __m, __m64 __count) { return (__m64)__builtin_ia32_psllw((__v4hi)__m, __count); } /// Left-shifts each 16-bit signed integer element of a 64-bit integer /// vector of [4 x i16] by the number of bits specified by a 32-bit integer. /// The lower 16 bits of the results are packed into a 64-bit integer vector /// of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSLLW </c> instruction. /// /// \param __m /// A 64-bit integer vector of [4 x i16]. /// \param __count /// A 32-bit integer value. /// \returns A 64-bit integer vector of [4 x i16] containing the left-shifted /// values. If \a __count is greater or equal to 16, the result is set to all /// 0. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_slli_pi16(__m64 __m, int __count) { return (__m64)__builtin_ia32_psllwi((__v4hi)__m, __count); } /// Left-shifts each 32-bit signed integer element of the first /// parameter, which is a 64-bit integer vector of [2 x i32], by the number /// of bits specified by the second parameter, which is a 64-bit integer. The /// lower 32 bits of the results are packed into a 64-bit integer vector of /// [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSLLD </c> instruction. /// /// \param __m /// A 64-bit integer vector of [2 x i32]. /// \param __count /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \returns A 64-bit integer vector of [2 x i32] containing the left-shifted /// values. If \a __count is greater or equal to 32, the result is set to all /// 0. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sll_pi32(__m64 __m, __m64 __count) { return (__m64)__builtin_ia32_pslld((__v2si)__m, __count); } /// Left-shifts each 32-bit signed integer element of a 64-bit integer /// vector of [2 x i32] by the number of bits specified by a 32-bit integer. /// The lower 32 bits of the results are packed into a 64-bit integer vector /// of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSLLD </c> instruction. /// /// \param __m /// A 64-bit integer vector of [2 x i32]. /// \param __count /// A 32-bit integer value. /// \returns A 64-bit integer vector of [2 x i32] containing the left-shifted /// values. If \a __count is greater or equal to 32, the result is set to all /// 0. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_slli_pi32(__m64 __m, int __count) { return (__m64)__builtin_ia32_pslldi((__v2si)__m, __count); } /// Left-shifts the first 64-bit integer parameter by the number of bits /// specified by the second 64-bit integer parameter. The lower 64 bits of /// result are returned. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSLLQ </c> instruction. /// /// \param __m /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \param __count /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \returns A 64-bit integer vector containing the left-shifted value. If /// \a __count is greater or equal to 64, the result is set to 0. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sll_si64(__m64 __m, __m64 __count) { return (__m64)__builtin_ia32_psllq((__v1di)__m, __count); } /// Left-shifts the first parameter, which is a 64-bit integer, by the /// number of bits specified by the second parameter, which is a 32-bit /// integer. The lower 64 bits of result are returned. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSLLQ </c> instruction. /// /// \param __m /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \param __count /// A 32-bit integer value. /// \returns A 64-bit integer vector containing the left-shifted value. If /// \a __count is greater or equal to 64, the result is set to 0. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_slli_si64(__m64 __m, int __count) { return (__m64)__builtin_ia32_psllqi((__v1di)__m, __count); } /// Right-shifts each 16-bit integer element of the first parameter, /// which is a 64-bit integer vector of [4 x i16], by the number of bits /// specified by the second parameter, which is a 64-bit integer. /// /// High-order bits are filled with the sign bit of the initial value of each /// 16-bit element. The 16-bit results are packed into a 64-bit integer /// vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRAW </c> instruction. /// /// \param __m /// A 64-bit integer vector of [4 x i16]. /// \param __count /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \returns A 64-bit integer vector of [4 x i16] containing the right-shifted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sra_pi16(__m64 __m, __m64 __count) { return (__m64)__builtin_ia32_psraw((__v4hi)__m, __count); } /// Right-shifts each 16-bit integer element of a 64-bit integer vector /// of [4 x i16] by the number of bits specified by a 32-bit integer. /// /// High-order bits are filled with the sign bit of the initial value of each /// 16-bit element. The 16-bit results are packed into a 64-bit integer /// vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRAW </c> instruction. /// /// \param __m /// A 64-bit integer vector of [4 x i16]. /// \param __count /// A 32-bit integer value. /// \returns A 64-bit integer vector of [4 x i16] containing the right-shifted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_srai_pi16(__m64 __m, int __count) { return (__m64)__builtin_ia32_psrawi((__v4hi)__m, __count); } /// Right-shifts each 32-bit integer element of the first parameter, /// which is a 64-bit integer vector of [2 x i32], by the number of bits /// specified by the second parameter, which is a 64-bit integer. /// /// High-order bits are filled with the sign bit of the initial value of each /// 32-bit element. The 32-bit results are packed into a 64-bit integer /// vector of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRAD </c> instruction. /// /// \param __m /// A 64-bit integer vector of [2 x i32]. /// \param __count /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \returns A 64-bit integer vector of [2 x i32] containing the right-shifted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_sra_pi32(__m64 __m, __m64 __count) { return (__m64)__builtin_ia32_psrad((__v2si)__m, __count); } /// Right-shifts each 32-bit integer element of a 64-bit integer vector /// of [2 x i32] by the number of bits specified by a 32-bit integer. /// /// High-order bits are filled with the sign bit of the initial value of each /// 32-bit element. The 32-bit results are packed into a 64-bit integer /// vector of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRAD </c> instruction. /// /// \param __m /// A 64-bit integer vector of [2 x i32]. /// \param __count /// A 32-bit integer value. /// \returns A 64-bit integer vector of [2 x i32] containing the right-shifted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_srai_pi32(__m64 __m, int __count) { return (__m64)__builtin_ia32_psradi((__v2si)__m, __count); } /// Right-shifts each 16-bit integer element of the first parameter, /// which is a 64-bit integer vector of [4 x i16], by the number of bits /// specified by the second parameter, which is a 64-bit integer. /// /// High-order bits are cleared. The 16-bit results are packed into a 64-bit /// integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRLW </c> instruction. /// /// \param __m /// A 64-bit integer vector of [4 x i16]. /// \param __count /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \returns A 64-bit integer vector of [4 x i16] containing the right-shifted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_srl_pi16(__m64 __m, __m64 __count) { return (__m64)__builtin_ia32_psrlw((__v4hi)__m, __count); } /// Right-shifts each 16-bit integer element of a 64-bit integer vector /// of [4 x i16] by the number of bits specified by a 32-bit integer. /// /// High-order bits are cleared. The 16-bit results are packed into a 64-bit /// integer vector of [4 x i16]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRLW </c> instruction. /// /// \param __m /// A 64-bit integer vector of [4 x i16]. /// \param __count /// A 32-bit integer value. /// \returns A 64-bit integer vector of [4 x i16] containing the right-shifted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_srli_pi16(__m64 __m, int __count) { return (__m64)__builtin_ia32_psrlwi((__v4hi)__m, __count); } /// Right-shifts each 32-bit integer element of the first parameter, /// which is a 64-bit integer vector of [2 x i32], by the number of bits /// specified by the second parameter, which is a 64-bit integer. /// /// High-order bits are cleared. The 32-bit results are packed into a 64-bit /// integer vector of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRLD </c> instruction. /// /// \param __m /// A 64-bit integer vector of [2 x i32]. /// \param __count /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \returns A 64-bit integer vector of [2 x i32] containing the right-shifted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_srl_pi32(__m64 __m, __m64 __count) { return (__m64)__builtin_ia32_psrld((__v2si)__m, __count); } /// Right-shifts each 32-bit integer element of a 64-bit integer vector /// of [2 x i32] by the number of bits specified by a 32-bit integer. /// /// High-order bits are cleared. The 32-bit results are packed into a 64-bit /// integer vector of [2 x i32]. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRLD </c> instruction. /// /// \param __m /// A 64-bit integer vector of [2 x i32]. /// \param __count /// A 32-bit integer value. /// \returns A 64-bit integer vector of [2 x i32] containing the right-shifted /// values. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_srli_pi32(__m64 __m, int __count) { return (__m64)__builtin_ia32_psrldi((__v2si)__m, __count); } /// Right-shifts the first 64-bit integer parameter by the number of bits /// specified by the second 64-bit integer parameter. /// /// High-order bits are cleared. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRLQ </c> instruction. /// /// \param __m /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \param __count /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \returns A 64-bit integer vector containing the right-shifted value. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_srl_si64(__m64 __m, __m64 __count) { return (__m64)__builtin_ia32_psrlq((__v1di)__m, __count); } /// Right-shifts the first parameter, which is a 64-bit integer, by the /// number of bits specified by the second parameter, which is a 32-bit /// integer. /// /// High-order bits are cleared. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PSRLQ </c> instruction. /// /// \param __m /// A 64-bit integer vector interpreted as a single 64-bit integer. /// \param __count /// A 32-bit integer value. /// \returns A 64-bit integer vector containing the right-shifted value. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_srli_si64(__m64 __m, int __count) { return (__m64)__builtin_ia32_psrlqi((__v1di)__m, __count); } /// Performs a bitwise AND of two 64-bit integer vectors. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PAND </c> instruction. /// /// \param __m1 /// A 64-bit integer vector. /// \param __m2 /// A 64-bit integer vector. /// \returns A 64-bit integer vector containing the bitwise AND of both /// parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_and_si64(__m64 __m1, __m64 __m2) { return __builtin_ia32_pand((__v1di)__m1, (__v1di)__m2); } /// Performs a bitwise NOT of the first 64-bit integer vector, and then /// performs a bitwise AND of the intermediate result and the second 64-bit /// integer vector. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PANDN </c> instruction. /// /// \param __m1 /// A 64-bit integer vector. The one's complement of this parameter is used /// in the bitwise AND. /// \param __m2 /// A 64-bit integer vector. /// \returns A 64-bit integer vector containing the bitwise AND of the second /// parameter and the one's complement of the first parameter. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_andnot_si64(__m64 __m1, __m64 __m2) { return __builtin_ia32_pandn((__v1di)__m1, (__v1di)__m2); } /// Performs a bitwise OR of two 64-bit integer vectors. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> POR </c> instruction. /// /// \param __m1 /// A 64-bit integer vector. /// \param __m2 /// A 64-bit integer vector. /// \returns A 64-bit integer vector containing the bitwise OR of both /// parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_or_si64(__m64 __m1, __m64 __m2) { return __builtin_ia32_por((__v1di)__m1, (__v1di)__m2); } /// Performs a bitwise exclusive OR of two 64-bit integer vectors. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PXOR </c> instruction. /// /// \param __m1 /// A 64-bit integer vector. /// \param __m2 /// A 64-bit integer vector. /// \returns A 64-bit integer vector containing the bitwise exclusive OR of both /// parameters. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_xor_si64(__m64 __m1, __m64 __m2) { return __builtin_ia32_pxor((__v1di)__m1, (__v1di)__m2); } /// Compares the 8-bit integer elements of two 64-bit integer vectors of /// [8 x i8] to determine if the element of the first vector is equal to the /// corresponding element of the second vector. /// /// The comparison yields 0 for false, 0xFF for true. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PCMPEQB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8]. /// \param __m2 /// A 64-bit integer vector of [8 x i8]. /// \returns A 64-bit integer vector of [8 x i8] containing the comparison /// results. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cmpeq_pi8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pcmpeqb((__v8qi)__m1, (__v8qi)__m2); } /// Compares the 16-bit integer elements of two 64-bit integer vectors of /// [4 x i16] to determine if the element of the first vector is equal to the /// corresponding element of the second vector. /// /// The comparison yields 0 for false, 0xFFFF for true. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PCMPEQW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// \returns A 64-bit integer vector of [4 x i16] containing the comparison /// results. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cmpeq_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pcmpeqw((__v4hi)__m1, (__v4hi)__m2); } /// Compares the 32-bit integer elements of two 64-bit integer vectors of /// [2 x i32] to determine if the element of the first vector is equal to the /// corresponding element of the second vector. /// /// The comparison yields 0 for false, 0xFFFFFFFF for true. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PCMPEQD </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [2 x i32]. /// \param __m2 /// A 64-bit integer vector of [2 x i32]. /// \returns A 64-bit integer vector of [2 x i32] containing the comparison /// results. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cmpeq_pi32(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pcmpeqd((__v2si)__m1, (__v2si)__m2); } /// Compares the 8-bit integer elements of two 64-bit integer vectors of /// [8 x i8] to determine if the element of the first vector is greater than /// the corresponding element of the second vector. /// /// The comparison yields 0 for false, 0xFF for true. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PCMPGTB </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [8 x i8]. /// \param __m2 /// A 64-bit integer vector of [8 x i8]. /// \returns A 64-bit integer vector of [8 x i8] containing the comparison /// results. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cmpgt_pi8(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pcmpgtb((__v8qi)__m1, (__v8qi)__m2); } /// Compares the 16-bit integer elements of two 64-bit integer vectors of /// [4 x i16] to determine if the element of the first vector is greater than /// the corresponding element of the second vector. /// /// The comparison yields 0 for false, 0xFFFF for true. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PCMPGTW </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [4 x i16]. /// \param __m2 /// A 64-bit integer vector of [4 x i16]. /// \returns A 64-bit integer vector of [4 x i16] containing the comparison /// results. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cmpgt_pi16(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pcmpgtw((__v4hi)__m1, (__v4hi)__m2); } /// Compares the 32-bit integer elements of two 64-bit integer vectors of /// [2 x i32] to determine if the element of the first vector is greater than /// the corresponding element of the second vector. /// /// The comparison yields 0 for false, 0xFFFFFFFF for true. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PCMPGTD </c> instruction. /// /// \param __m1 /// A 64-bit integer vector of [2 x i32]. /// \param __m2 /// A 64-bit integer vector of [2 x i32]. /// \returns A 64-bit integer vector of [2 x i32] containing the comparison /// results. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_cmpgt_pi32(__m64 __m1, __m64 __m2) { return (__m64)__builtin_ia32_pcmpgtd((__v2si)__m1, (__v2si)__m2); } /// Constructs a 64-bit integer vector initialized to zero. /// /// \headerfile <x86intrin.h> /// /// This intrinsic corresponds to the <c> PXOR </c> instruction. /// /// \returns An initialized 64-bit integer vector with all elements set to zero. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_setzero_si64(void) { return __extension__ (__m64){ 0LL }; } /// Constructs a 64-bit integer vector initialized with the specified /// 32-bit integer values. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __i1 /// A 32-bit integer value used to initialize the upper 32 bits of the /// result. /// \param __i0 /// A 32-bit integer value used to initialize the lower 32 bits of the /// result. /// \returns An initialized 64-bit integer vector. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_set_pi32(int __i1, int __i0) { return (__m64)__builtin_ia32_vec_init_v2si(__i0, __i1); } /// Constructs a 64-bit integer vector initialized with the specified /// 16-bit integer values. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __s3 /// A 16-bit integer value used to initialize bits [63:48] of the result. /// \param __s2 /// A 16-bit integer value used to initialize bits [47:32] of the result. /// \param __s1 /// A 16-bit integer value used to initialize bits [31:16] of the result. /// \param __s0 /// A 16-bit integer value used to initialize bits [15:0] of the result. /// \returns An initialized 64-bit integer vector. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_set_pi16(short __s3, short __s2, short __s1, short __s0) { return (__m64)__builtin_ia32_vec_init_v4hi(__s0, __s1, __s2, __s3); } /// Constructs a 64-bit integer vector initialized with the specified /// 8-bit integer values. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __b7 /// An 8-bit integer value used to initialize bits [63:56] of the result. /// \param __b6 /// An 8-bit integer value used to initialize bits [55:48] of the result. /// \param __b5 /// An 8-bit integer value used to initialize bits [47:40] of the result. /// \param __b4 /// An 8-bit integer value used to initialize bits [39:32] of the result. /// \param __b3 /// An 8-bit integer value used to initialize bits [31:24] of the result. /// \param __b2 /// An 8-bit integer value used to initialize bits [23:16] of the result. /// \param __b1 /// An 8-bit integer value used to initialize bits [15:8] of the result. /// \param __b0 /// An 8-bit integer value used to initialize bits [7:0] of the result. /// \returns An initialized 64-bit integer vector. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_set_pi8(char __b7, char __b6, char __b5, char __b4, char __b3, char __b2, char __b1, char __b0) { return (__m64)__builtin_ia32_vec_init_v8qi(__b0, __b1, __b2, __b3, __b4, __b5, __b6, __b7); } /// Constructs a 64-bit integer vector of [2 x i32], with each of the /// 32-bit integer vector elements set to the specified 32-bit integer /// value. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __i /// A 32-bit integer value used to initialize each vector element of the /// result. /// \returns An initialized 64-bit integer vector of [2 x i32]. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_set1_pi32(int __i) { return _mm_set_pi32(__i, __i); } /// Constructs a 64-bit integer vector of [4 x i16], with each of the /// 16-bit integer vector elements set to the specified 16-bit integer /// value. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __w /// A 16-bit integer value used to initialize each vector element of the /// result. /// \returns An initialized 64-bit integer vector of [4 x i16]. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_set1_pi16(short __w) { return _mm_set_pi16(__w, __w, __w, __w); } /// Constructs a 64-bit integer vector of [8 x i8], with each of the /// 8-bit integer vector elements set to the specified 8-bit integer value. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __b /// An 8-bit integer value used to initialize each vector element of the /// result. /// \returns An initialized 64-bit integer vector of [8 x i8]. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_set1_pi8(char __b) { return _mm_set_pi8(__b, __b, __b, __b, __b, __b, __b, __b); } /// Constructs a 64-bit integer vector, initialized in reverse order with /// the specified 32-bit integer values. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __i0 /// A 32-bit integer value used to initialize the lower 32 bits of the /// result. /// \param __i1 /// A 32-bit integer value used to initialize the upper 32 bits of the /// result. /// \returns An initialized 64-bit integer vector. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_setr_pi32(int __i0, int __i1) { return _mm_set_pi32(__i1, __i0); } /// Constructs a 64-bit integer vector, initialized in reverse order with /// the specified 16-bit integer values. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __w0 /// A 16-bit integer value used to initialize bits [15:0] of the result. /// \param __w1 /// A 16-bit integer value used to initialize bits [31:16] of the result. /// \param __w2 /// A 16-bit integer value used to initialize bits [47:32] of the result. /// \param __w3 /// A 16-bit integer value used to initialize bits [63:48] of the result. /// \returns An initialized 64-bit integer vector. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_setr_pi16(short __w0, short __w1, short __w2, short __w3) { return _mm_set_pi16(__w3, __w2, __w1, __w0); } /// Constructs a 64-bit integer vector, initialized in reverse order with /// the specified 8-bit integer values. /// /// \headerfile <x86intrin.h> /// /// This intrinsic is a utility function and does not correspond to a specific /// instruction. /// /// \param __b0 /// An 8-bit integer value used to initialize bits [7:0] of the result. /// \param __b1 /// An 8-bit integer value used to initialize bits [15:8] of the result. /// \param __b2 /// An 8-bit integer value used to initialize bits [23:16] of the result. /// \param __b3 /// An 8-bit integer value used to initialize bits [31:24] of the result. /// \param __b4 /// An 8-bit integer value used to initialize bits [39:32] of the result. /// \param __b5 /// An 8-bit integer value used to initialize bits [47:40] of the result. /// \param __b6 /// An 8-bit integer value used to initialize bits [55:48] of the result. /// \param __b7 /// An 8-bit integer value used to initialize bits [63:56] of the result. /// \returns An initialized 64-bit integer vector. static __inline__ __m64 __DEFAULT_FN_ATTRS _mm_setr_pi8(char __b0, char __b1, char __b2, char __b3, char __b4, char __b5, char __b6, char __b7) { return _mm_set_pi8(__b7, __b6, __b5, __b4, __b3, __b2, __b1, __b0); } #undef __DEFAULT_FN_ATTRS /* Aliases for compatibility. */ #define _m_empty _mm_empty #define _m_from_int _mm_cvtsi32_si64 #define _m_from_int64 _mm_cvtsi64_m64 #define _m_to_int _mm_cvtsi64_si32 #define _m_to_int64 _mm_cvtm64_si64 #define _m_packsswb _mm_packs_pi16 #define _m_packssdw _mm_packs_pi32 #define _m_packuswb _mm_packs_pu16 #define _m_punpckhbw _mm_unpackhi_pi8 #define _m_punpckhwd _mm_unpackhi_pi16 #define _m_punpckhdq _mm_unpackhi_pi32 #define _m_punpcklbw _mm_unpacklo_pi8 #define _m_punpcklwd _mm_unpacklo_pi16 #define _m_punpckldq _mm_unpacklo_pi32 #define _m_paddb _mm_add_pi8 #define _m_paddw _mm_add_pi16 #define _m_paddd _mm_add_pi32 #define _m_paddsb _mm_adds_pi8 #define _m_paddsw _mm_adds_pi16 #define _m_paddusb _mm_adds_pu8 #define _m_paddusw _mm_adds_pu16 #define _m_psubb _mm_sub_pi8 #define _m_psubw _mm_sub_pi16 #define _m_psubd _mm_sub_pi32 #define _m_psubsb _mm_subs_pi8 #define _m_psubsw _mm_subs_pi16 #define _m_psubusb _mm_subs_pu8 #define _m_psubusw _mm_subs_pu16 #define _m_pmaddwd _mm_madd_pi16 #define _m_pmulhw _mm_mulhi_pi16 #define _m_pmullw _mm_mullo_pi16 #define _m_psllw _mm_sll_pi16 #define _m_psllwi _mm_slli_pi16 #define _m_pslld _mm_sll_pi32 #define _m_pslldi _mm_slli_pi32 #define _m_psllq _mm_sll_si64 #define _m_psllqi _mm_slli_si64 #define _m_psraw _mm_sra_pi16 #define _m_psrawi _mm_srai_pi16 #define _m_psrad _mm_sra_pi32 #define _m_psradi _mm_srai_pi32 #define _m_psrlw _mm_srl_pi16 #define _m_psrlwi _mm_srli_pi16 #define _m_psrld _mm_srl_pi32 #define _m_psrldi _mm_srli_pi32 #define _m_psrlq _mm_srl_si64 #define _m_psrlqi _mm_srli_si64 #define _m_pand _mm_and_si64 #define _m_pandn _mm_andnot_si64 #define _m_por _mm_or_si64 #define _m_pxor _mm_xor_si64 #define _m_pcmpeqb _mm_cmpeq_pi8 #define _m_pcmpeqw _mm_cmpeq_pi16 #define _m_pcmpeqd _mm_cmpeq_pi32 #define _m_pcmpgtb _mm_cmpgt_pi8 #define _m_pcmpgtw _mm_cmpgt_pi16 #define _m_pcmpgtd _mm_cmpgt_pi32 #endif /* __MMINTRIN_H */